MC9S12E128V1 Datasheet, PDF (131/606 Pages) Freescale Semiconductor, Inc – Microcontrollers

3.3.1.3
Chapter 3 Port Integration Module (PIM9E128V1)
Port AD Data Direction Register (DDRAD)
7
R
DDRAD15
W
Reset
0
6
DDRAD14
0
5
DDRAD13
0
4
DDRAD12
0
3
DDRAD11
0
2
DDRAD10
0
1
DDRAD9
0
0
DDRAD8
0
7
R
DDRAD7
W
Reset
0
6
DDRAD6
5
DDRAD5
4
DDRAD4
3
DDRAD3
2
DDRAD2
0
0
0
0
0
Figure 3-4. Port AD Data Direction Register (DDRAD)
1
DDRAD1
0
0
DDRAD0
0
Read: Anytime. Write: Anytime.
This register configures port pins PAD[15:0] as either input or output.
If a data direction bit is 0 (pin configured as input), then a read value on PTADx depends on the associated
ATDDIEN0(1) bit. If the associated ATDDIEN0(1) bit is set to 1 (digital input buffer is enabled), a read
on PTADx returns the value on port AD pin. If the associated ATDDIEN0(1) bit is set to 0 (digital input
buffer is disabled), a read on PTADx returns a 1.
Table 3-3. DDRAD Field Descriptions
Field
15:0
Data Direction Port AD
DDRAD[15:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
131