MC13201_07 Datasheet, PDF (13/28 Pages) Freescale Semiconductor, Inc – 2.4 GHz Low Power Transceiver for the IEEE® 802.15.4 Standard

6.2.2 SPI Transaction Operation
Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13201 requires that a complete
SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion
of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the
transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and
identifies the access as being a read or write operation. In this context, a write is data written to the
MC13201 and a read is data written to the SPI master. The following SPI bursts will be either the write
data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).
Although the SPI bus is capable of sending data simultaneously between master and slave, the MC13201
never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to
a larger number depending on the type of access. The number of payload bytes sent will always be an even
integer. After the final SPI burst, CE is negated to high to signal the end of the transaction. Refer to the
MC13201 Reference Manual, (MC13201RM) for more details on SPI registers and transaction types.
An example SPI read transaction with a 2-byte payload is shown in Figure 9.
CE
Clock Burst
SPICLK
MISO
Valid
Valid
MOSI
Valid
Header
Read data
Figure 9. SPI Read Transaction Diagram
MC13201 Technical Data, Rev. 1.1,
Freescale Semiconductor
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