MCF548X Datasheet, PDF (12/28 Pages) Freescale Semiconductor, Inc – Microprocessor Electrical Characteristics

SDRAM Bus
Table 11. SDR Timing Specifications
Symbol
Characteristic
Min
Max
Unit Notes
Frequency of Operation
0
SD1 Clock Period (t_CK)
7.52
SD2 Clock Skew (t_SK)
SD3 Pulse Width High (t_CKH)
0.45
SD4 Pulse Width Low (t_CKL)
0.45
SD5 Address, CKE, CAS, RAS, WE, BA, CS - Output Valid (t_CMV)
133
Mhz
1
12
ns
2
TBD
0.55
0.55
SDCLK ³
SDCLK ⁴
0.5 × SDCLK + ns
1.0ns
SD6 Address, CKE, CAS, RAS, WE, BA, CS - Output Hold (t_CMH)
2.0
ns
SD7 SDRDQS Output Valid (t_DQSOV)
Self timed
ns
5
SD8 SDDQS[3:0] input setup relative to SDCLK (t_DQSIS)
0.25 × SDCLK 0.40 × SDCLK ns
6
SD9 SDDQS[3:0] input hold relative to SDCLK (t_DQSIH)
Does not apply. 0.5 SDCLK fixed width.
7
SD10 Data Input Setup relative to SDCLK (reference only) (t_DIS) 0.25 × SDCLK
ns
8
SD11
SD12
Data Input Hold relative to SDCLK (reference only) (t_DIH)
Data and Data Mask Output Valid (t_DV)
1.0
ns
0.75 × SDCLK ns
+0.500ns
SD13 Data and Data Mask Output Hold (t_DH)
1.5
ns
NOTES:
1 _{The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external}
reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock
operates at the same frequency as the internal bus clock. Please see the PLL chapter of the MCF548X Reference Manual
for more information on setting the SDRAM clock rate.
2 _{SDCLK is one SDRAM clock in (ns).}
3 _{Pulse width high plus pulse width low cannot exceed min and max clock period.}
4 _{Pulse width high plus pulse width low cannot exceed min and max clock period.}
5 _{SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle}
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each
data beat.
6 _{SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle}
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each
data beat.
7 _{The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge}
does not affect the memory controller.
8 _{Since a read cycle in SDR mode still uses the DQS circuit within the MCF548X, it is most critical that the data valid window}
be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input
setup spec is just provided as guidance.
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4
12
Freescale Semiconductor