MCF5271 Datasheet, PDF (11/40 Pages) Freescale Semiconductor, Inc – Integrated Microprocessor Hardware Specification

Design Recommendations
Table 3. Synchronous DRAM Signal Connections
Signal
Description
SD_SRAS
SD_SCAS
DRAMW
SD_CS[1:0]
SD_CKE
BS[3:0]
CLKOUT
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be
latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM
SD_SRAS. Do not confuse SD_SRAS with the DRAM controller’s SD_CS[1:0], which should not
be interfaced to the SDRAM SD_SRAS signals.
Synchronous column address strobe. Indicates a valid column address is present and can be
latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled
SD_SCAS on the SDRAM.
DRAM read/write. Asserted for write operations and negated for read operations.
Row address strobe. Select each memory block of SDRAMs connected to the MCF5271. One
SD_CS signal selects one SDRAM block and connects to the corresponding CS signals.
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of
SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can
enter a power-down mode where operations are suspended or they can enter self-refresh mode.
SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing,
setting COC allows SD_CKE to provide command-bit functionality.
Column address strobe. For synchronous operation, BS[3:0] function as byte enables to the
SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.
Bus clock output. Connects to the CLK input of SDRAMs.
5.7.1.2 Address Multiplexing
See the SDRAM controller module chapter in the MCF5271 Reference Manual for details on address
multiplexing.
5.7.2 Ethernet PHY Transceiver Connection
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3
standard defines and the FEC module supports 18 signals. These are shown in Table 4.
Table 4. MII Mode
Signal Description
Transmit clock
Transmit enable
Transmit data
Transmit error
Collision
Carrier sense
Receive clock
Receive enable
Receive data
MCF5271 Pin
ETXCLK
ETXEN
ETXD[3:0]
ETXER
ECOL
ECRS
ERXCLK
ERXDV
ERXD[3:0]
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 2
Freescale Semiconductor
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