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DSP56F803BU80 Datasheet, PDF (11/52 Pages) Freescale Semiconductor, Inc – Up to 40 MIPS at 80MHz core frequency | |||
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2.3 Clock and Phase Locked Loop Signals
Clock and Phase Locked Loop Signals
No. of
Pins
1
1
1
Signal
Name
EXTAL
XTAL
CLKO
Table 2-5 PLL and Clock
Signal
Type
Input
Input/
Output
State During
Reset
Input
Chip-driven
Signal Description
External Crystal Oscillator InputâThis input should be connected to
an 8MHz external crystal or ceramic resonator. For more information,
please refer to Section 3.5.
Crystal Oscillator OutputâThis output should be connected to an
8MHz external crystal or ceramic resonator. For more information,
please refer to Section 3.5.
Output
Chip-driven
This pin can also be connected to an external clock source. For more
information, please refer to Section 3.5.3.
Clock OutputâThis pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select Register
(CLKOSR), the user can select between outputting a version of the
signal applied to XTAL and a version of the deviceâs master clock at the
output of the PLL. The clock frequency on this pin can also be disabled
by programming the CLKOSEL[4:0] bits in CLKOSR.
2.4 Address, Data, and Bus Control Signals
Table 2-6 Address Bus Signals
No. of
Pins
6
2
Signal
Name
A0âA5
A6âA7
Signal
Type
Output
Output
State During
Reset
Tri-stated
Tri-stated
Signal Description
Address BusâA0âA5 specify the address for external Program or Data
memory accesses.
Address BusâA6âA7 specify the address for external Program or Data
memory accesses.
GPIOE2â Input/O
GPIOE3 utput
Input
Port E GPIOâThese two pins are General Purpose I/O (GPIO) pins that
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8âA15 Output Tri-stated Address BusâA8âA15 specify the address for external Program or
Data memory accesses.
GPIOA0â Input/O
GPIOA7 utput
Input
Port A GPIOâThese eight pins are General Purpose I/O (GPIO) pins
that can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
56F803 Technical Data, Rev. 16
Freescale Semiconductor
11
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