MCIMX25_1004 Datasheet, PDF (107/144 Pages) Freescale Semiconductor, Inc – i.MX25 Applications Processor for Consumer and Industrial Products

Table 80. SSI Receiver Timing with Internal Clock (continued)
ID
SS48
SS49
SS50
SS51
Parameter
Oversampling clock high period
Oversampling clock rise time
Oversampling clock low period
Oversampling clock fall time
Min.
6.0
—
6.0
—
Max.
Unit
—
ns
3.0
ns
—
ns
3.0
ns
Note:
• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
• All timings are on pads when SSI is being used for a data transfer.
• ”Tx” and “Rx” refer to the transmit and receive sections of the SSI.
• For internal frame sync operation using external clock, the FS timing is the same as that of Tx Data (for example, during AC97
mode of operation).
3.7.17.3 SSI Transmitter Timing with External Clock
Figure 80 shows the timing for the SSI transmitter with external clock. Table 81 describes the timing
parameters (SS22-SS46) shown in the figure.
SS23
SS22
SS25
SS26
SS24
AUDn_TXC
(Input)
AUDn_TXFS (bl)
(Input)
SS27
SS31
SS29
SS33
AUDn_TXFS (wl)
(Input)
AUDn_TXD
(Output)
AUDn_RXD
(Input)
SS37
SS44
SS38
SS45
SS39
Note: SRXD Input in Synchronous mode only
SS46
Figure 80. SSI Transmitter with External Clock Timing Diagram
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3
Freescale Semiconductor
107