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MC9S08GW64 Datasheet, PDF (1/38 Pages) Freescale Semiconductor, Inc – Covers: MC9S08GW64 and MC9S08GW32 | |||
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Freescale Semiconductor
Data Sheet: Advance Information
An Energy Efficient Solution by Freescale
Document Number: MC9S08GW64
Rev. 1, 5/2010
MC9S08GW64 Series
Covers: MC9S08GW64 and
MC9S08GW64 80-LQFP
Case 917A
64-LQFP
Case 840F
14 Ã 14
10 Ã 10
MC9S08GW32
8-Bit HCS08 Central Processor Unit (CPU)
comparator can be used as hardware breakpoint. Full mode,
Comparator A compares address and Comparator B compares data.
Supports both tag and force breakpoints
â New version of S08 core with same performace as traditional S08 and
lower power
â Up to 20 MHz CPU at 3.6 V to 2.15 V and up to 10 MHz CPU at 2.15
V to 1.8 V, across temperature range of â40 °C to 85 °C
â HC08 instruction set with added BGND instruction
â Support for up to 48 interrupt/reset sources
On-Chip Memory
â Flash read/program/erase over full operating voltage and temperature
â Random-access memory (RAM)
â Security circuitry to prevent unauthorized access to RAM and flash
contents
Power-Saving Modes
â Two low power stop modes and reduced power wait mode
â Low power run and wait modes allow peripherals to run while voltage
regulator is in standby
â Peripheral clock gating register can disable clocks to unused modules,
thereby reducing currents
â Very low power external oscillator that can be used in stop2 or stop3
modes to provide accurate clock source to real time counter
â 6 μs typical wakeup time from stop3 mode
Clock Source Options
Peripherals
â LCD â up to 4Ã40 or 8Ã36 LCD driver with internal charge pump and
option to provide an internally regulated LCD reference that can be
trimmed for contrast control
â ADC16 â two analog-to-digital converters; 16-bit resolution; one
dedicated differential per ADC; up to 16-ch; up to 2.5 μs conversion
time for 12-bit mode; automatic compare function; hardware
averaging; calibration registers; temperature sensor; internal bandgap
reference channel; operation in stop3; fully functional from 3.6 V to 1.8
V
â PRACMP âthree rail to rail programmable reference analog
comparator; up to 8 inputs; on-chip programmable reference generator
output; selectable interrupt on rising, falling, or either edge of
comparator output; operation in stop3
â SCI â four full duplex non-return to zero (NRZ); LIN master extended
break generation; LIN slave extended break detection; wakeup on
active edge; SCI0 designed for AMR operation; TxD of SCI1 and SCI2
can be modulated with timers and RxD can recieved through
PRACMP;
â SPIâ three full-duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or LSB-first
shifting; SPI0 designed for AMR opeartion
â IIC â up to 100 kbps with maximum bus loading; multi-master
operation; programmable slave address; interrupt driven byte-by-byte
â Oscillator (XOSC1) â Loop-control Pierce oscillator; Crystal or
ceramic resonator of 32.768 kHz; Clock source for iRTC or ICS
â Oscillator (XOSC2) â Loop-control Pierce oscillator; Crystal or
ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz;
optional clock source for ICS
â Internal Clock Source (ICS) â Internal clock source module
containing a frequency-locked-loop (FLL) controlled by internal or
external reference (XOSC1, XOSC2); precision trimming of internal
reference allows 0.2% resolution and 2% deviation over temperature
and voltage; supporting CPU/bus frequencies from 1 MHz to 20 MHz
System Protection
data transfer; supporting broadcast mode and 10-bit addressing;
supporting SM BUS functionality; can wake from stop3
â FTM â 2-channel FTMs; selectable input capture, output compare, or
buffered edge- or center-aligned PWM on each channel
â IRTC â independent real-time clock, independent power domain, 32
bytes RAM, 32.768 kHz input clock optional output to ICS, hardware
calendar, hardware compensation due to crystal or temperature
characteristics, tamper detection and indicator
â PCRC â 16/32 bit programmable cyclic redundancy check for
high-speed CRC calculation
â MTIM â two 8-bit and one 16-bit timers; configurable clock inputs
and interrupt generation on overflow
â Watchdog computer operating properly (COP) reset with option to run
from dedicated 1 kHz internal clock source or bus clock
â Low-voltage warning with interrupt
â Low-voltage detection with reset or interrupt
â Illegal opcode and illegal address detection with reset
â Flash block protection
Development Support
â Single-wire background debug interface
â Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus 3 more breakpoints in breakpoint unit)
â PDB â programmable delay block; optimized for scheduling ADC
conversions
â PCNT â position counter; working in stop3 mode without waking
CPU; can be used to generate waveforms like timer
Input/Output
â 57 GPIOs including one output-only pin
â Eight KBI interrupts with selectable polarity
â Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins.
Package Options
â Breakpoint (BKPT) debug module containing three comparators (A, B,
and C) with ability to match addresses in 64 KB space. Each
â 80-pin LQFP, 64-pin LQFP
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2010. All rights reserved.
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
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