F71805 Datasheet, PDF (68/94 Pages) Feature Integration Technology Inc. – Super H/W Monitor + LPC IO

F71805
7-0 PWM_DUTY1
R/W FFh When FAN1 control is at PWM Duty-cycle mode, this value represents the
duty-cycle.
When FAN1 control is at DC mode, this value represents the DC voltage
output. Each step (LSB) is VCC / 256.
This register is programmable at Manual mode.
At SPEED or TEMPERATURE mode, this register reflects current
FANPWM1 duty-cycle.
7.6.3.34 FAN2 OPERATING Control Register -- Index 70h
Bit
Name
R/W Default
Description
7 FAN2_SKIP
R
6 Reserved
-
5 ^{FAN2_FORCE_MONI} R/W
TOR
4 ^FAN2_DC_MODE R/W
3 F2_LATCH_FULL
2 F2_KEEP_STOP
1-0 F2_MODE
R/W
R/W
R/W
- When this bit is set to 1, FAN2 is not monitored.
When this bit is set to 0, FAN2 is monitored.
- Reserved.
0 ^{Set to 1, FAN2 speed is monitored every monitor cycle even the fan is}
stopped. Set to 0, FAN2 speed will not be monitored at the next monitor cycle if
the fan is stopped.
0 ^{Set to 1, FAN2 control is set to DC mode.}
Set to 0, FAN2 control is set to PWM duty-cycle mode.
0 Set to 1, current FAN2 COUNT will be bypass to F2_FULL_SPEED.
0 Set to 1, keep FANPWM2 duty-cycle decrease to STOP DUTY and hold.
00 00: FAN2 operates in SPEED mode. FANPWM duty-cycle is automatically
adjusted according to FAN EXPECT register.
01: FAN2 operates in TEMPERATURE mode. FANPWM duty-cycle is
automatically adjusted according to current temperature,
1x: FAN2 operates in MANUAL mode. Software set the FANPWM duty-cycle
directly.
7.6.3.35 FANPWM2 START UP DUTY-CYCLE  Index 71h
Bit
Name
7-0 F2_START_DUTY
R/W Default
Description
R/W 30h FANPWM2 will increase duty-cycle from 0 to this value directly.
7.6.3.36 FANPWM2 STOP DUTY-CYCLE  Index 72h
Bit
Name
7-0 F2_STOP_DUTY
R/W Default
Description
R/W 25h FANPWM2 will decreasing duty-cycle to 0 from this value directly or keep
duty-cycle in this value when F2_KEEP_STOP set to 1.
7.6.3.37 FANPWM2 Output Frequency Control  Index 73h
Bit
Name
7 PWM2_DIV[7]
R/W Default
Description
R/W 80h Set to 1, PRECLK(Pre-Clock) = 48M Hz ;
Set to 0, PRECLK
= 1M Hz .
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Dec., 2006
V0.25P