F71805 Datasheet, PDF (49/94 Pages) Feature Integration Technology Inc. – Super H/W Monitor + LPC IO

4-3 IRMODE
2 HDUPLX
1 TXINV_IR
0 RXINV_IR
F71805
R/W 00 00: disable IR function.
01: disable IR function.
10: IrDA function, active pulse is 1.6uS.
11: IrDA function, active pulse is 3/16 bit time.
R/W 1 0: SIR is in full duplex mode for loopbak test. TXW4C_IR and RXW4C_IR are
of no use.
1: SIR is in half duplex mode.
R/W 0 0: IRTX is in normal condition.
1: inverse the IRTX.
R/W 0 0: IRRX is in normal condition.
1: inverse the IRRX.
7.4.3 Device Registers
7.4.3.1 Receiver Buffer Register  Base + 0
Bit
Name
7-0 RBR
R/W Default
R 00h ^{The data received.}
Read only when LCR[7] is 0
Description
7.4.3.2 Transmitter Holding Register  Base + 0
Bit
Name
7-0 THR
R/W Default
W 00h ^{Data to be transmitted.}
Write only when LCR[7] is 0
Description
7.4.3.3 Divisor Latch (LSB)  Base + 0
Bit
Name
7-0 DLL
R/W Default
Description
R/W 01h ^{Baud generator divisor low byte.}
Access only when LCR[7] is 1.
7.4.3.4 Divisor Latch (MSB)  Base + 1
Bit
Name
7-0 DLM
R/W Default
Description
R/W 00h ^{Baud generator divisor high byte.}
Access only when LCR[7] is 1.
7.4.3.5 Interrupt Enable Register  Base + 1
Bit
Name
R/W Default
Description
47
Dec., 2006
V0.25P