F71883 Datasheet, PDF (52/133 Pages) Feature Integration Technology Inc. – Super Hardware Monitor + LPC I/O

F71883
Command register
The internal KBC operation is controlled by the KBC command byte (KCCB). The KCCB resides in I/O address
64h that is read with a 20h command and written with a 60h command data.
Bit
Name
R/W Default
Description
7 Reserved
-
- Reserved
6 Translate code
R/W 1 0: Pass un-translated scan code.
1: Translate scan code to IBM PC standard.
5 Disable Auxiliary R/W 0 1: Disable Auxiliary inhibit function.
Device
4 Disable Keyboard R/W 0 1: Disable keyboard inhibit function.
3 Reserved
-
- Reserved
2 System flag
R/W 1 0: The system is executing POST as a result of a cold boot.
1: The system is executing POST as a result of a shutdown or warm boot.
1 Enable Auxiliary R/W 1 0: Ao interrupt
Interrupt
1: A system interrupt is generated when a byte is placed in output buffer
(IRQ12).
0 Enable keyboard R/W 1 0:No interrupt
Interrupt
1: A system interrupt is generated when a byte is placed in output buffer
(IRQ1).
DATA register
The DATA register is an 8 bits register at I/O address 60h. the KBC used the output buffer to send the scan code
received from keyboard and data byte replay by command to the system.
Power on default <7:0> = 00000000 binary
7.7 SPI Interface
Communication between the two devices is handling the serial peripheral interface (SPI).
Every SPI system consist of one master and one or more slaves, where a master provides the
SPI clock and slave receives clock from the master.
This design is only master function, for basic signal, master-out/slave-in (MOSI),
master-in/slave-out (MISO), serial clock (SCK), and 4 slaves select (SS), are needed for SPI
interface. Each of slave select supports from 512kbits to 4096kbits flash is decided by
configuration register. Serial clock (SCK) signal frequency is varied from 24MHz to 187.5 KHz.
The serial data (MOSI) for SPI interface translates to depend on SCK rising edge or falling
edge is decided by configuration register.
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May, 2008
V0.27P