F71883 Datasheet, PDF (24/133 Pages) Feature Integration Technology Inc. – Super Hardware Monitor + LPC I/O

1-0 DRATE
W 10 Data rate select:
MFM
00: 500Kbps
01: 300Kbps
10: 250Kbps
11: 1Mbps
FM
250Kbps
150Kbps
125Kbps
illegal
F71883
Data (FIFO) Register  Base + 5
Bit
Name
R/W Default
Description
7-0 DATA
R/W 00h The FIFO is used to transfer all commands, data and status between controller
and the system. The Data Register consists of four status registers in a stack
with only one register presented to the data bus at a time. The FIFO is default
disabled and could be enabled via the CONFIGURE command.
Status Registers 0
Bit
Name
7-6 IC
5 SE
4 EC
3 NR
2 HD
1-0 DS
R/W Default
Description
R
- Interrupt code :
00: Normal termination of command.
01: Abnormal termination of command.
10: Invalid command.
11: Abnormal termination caused by poling.
R
- Seek end.
Set when a SEEK or RECALIBRATE or a READ or WRITE with implied seek
command is completed.
R
- Equipment check.
0: No error
1: When a fault signal is received form the FDD or the TRK0# signal fails to
occur after 77 step pulses.
R
- Not ready.
0: Drive is ready
1: Drive is not ready.
R
- Head address.
The current head address.
R
- Drive select.
00: Drive A selected.
01: Drive B selected.
10: Drive C selected.
11: Drive D selected.
Status Registers 1
Bit
Name
7 EN
6 DE
R/W Default
Description
R
- End of Track.
Set when the FDC tries to access a sector beyond the final sector of a cylinder.
R
- Data Error.
The FDC detect a CRC error in either the ID field or the data field of a sector.
-18-
May, 2008
V0.27P