LPV3000 Datasheet, PDF (1/2 Pages) Filtronic Compound Semiconductors – 2W Power PHEMT

Filtronic
Solid State
DRAIN PAD
(x4)
LP3000/LPV3000
2W Power PHEMT
FEATURES
• +33.5 dBm Typical Power at 18 GHz
• 7 dB Typical Power Gain at 18 GHz
• +30.5 dBm at 3.3V Battery Voltage
• Low Intermodulation Distortion
• 45% Power-Added-Efficiency at 18 GHz
SOURCE BOND
PAD (x2)
GATE PAD
(x4)
DIE SIZE: 28.3 x 16.5 mils (720 x 420 µm)
DIE THICKNESS: 2.6 mils (65 µm typ.)
BONDING PADS: 1.9 x 2.4 mils (50 x 60 µm typ.)
DESCRIPTION AND APPLICATIONS
The LP3000 is an Aluminum Gallium Arsenide / Indium Gallium Arsenide (AlGaAs/InGaAs) Pseudomorphic High Electron
Mobility Transistor (PHEMT), utilizing an Electron-Beam direct-write 0.25 µm by 3000 µm Schottky barrier gate. The
recessed “mushroom” gate structure minimizes parasitic gate-source and gate resistances. The epitaxial structure and
processing have been optimized for reliable high-power applications. The LP3000 also features Si₃N₄ passivation and is
available with plated source via-holes (LPV 3000) as an option for improved high-frequency performance. Also available in
a ceramic flanged package (P100) and ball grid array package.
Typical applications include commercial and military high-performance power amplifiers, including SATCOM uplink
transmitters, PCS/Cellular low-voltage high-efficiency output amplifiers, and medium-haul digital radio transmitters. The
LPV 3000/LP 3000 may be procured in a variety of grades, depending upon specific user requirements. Standard lot
screening is patterned after MIL-STD-19500, JANC grade. Space-level screening to FSS JANS grade is also available.
PERFORMANCE SPECIFICATIONS (T_A = 25°C)
SYMBOLS PARAMETERS
I_DSS
P_1dB
G_1dB
η_ADD
I_MAX
G_M
Saturated Drain-Source Current
V_DS = 2V V_GS = 0V
Output Power at 1dB Gain Compression
V_DS = 8.0V, I_DS = 50% I_DSS (LP. LPV)
f = 18 GHz
Power Gain at 1dB Gain Compression
V_DS = 8.0V, I_DS = 50% I_DSS (LP)
V_DS = 8.0V, I_DS = 50% I_DSS (LPV)
f = 18 GHz
f = 18 GHz
Power-Added Efficiency (typ. for Class A operation)
Maximum Drain-Source Current
Transconductance
V_DS = 2V V_GS = +1V
V_DS = 2V V_GS = 0V
V_P
Pinch-Off Voltage
I_GSO
Gate-Source Leakage Current
V_DS = 2V I_DS = 10mA
V_GS = -5V
BV_GS
Gate-Source Breakdown Voltage
I_GS = 15mA
BV_GD
Gate-Drain Breakdown Voltage
I_GD = 15mA
Θ_J
Thermal Resistivity
MIN TYP MAX UNITS
800 1060 1100 mA
33.0 33.5
dBm
4.0
6.0
dB
6.0
7.0
dB
45
%
1700
mA
725 900
mS
-0.25 -1.2 -2.0
V
15
125
µA
-12
-15
V
-12
-16
V
20
°C/W
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