CMP1617BAX-E Datasheet, PDF (5/12 Pages) FIDELIX – 1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM

CMP1617BAx-E
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level : 0.2 to VCC-0.2V
Input rising and falling time : 5ns
Input and output reference voltage : 0.5*VCCQ
Output load(see right) : CL=30pF+1TTL
CMOS LPRAM
30pf
1TTL
AC CHARACTERISTICS(VCC=2.7V~3.3V, Extended product : TA=-25 to 85’C)
Parameter List
Symbol
60ns
Speed Bins
70ns
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Min
Max
Min
Max
tRC
60
40k
70
40k
tAA
-
60
-
70
tCO
-
60
-
70
tOE
-
25
-
25
/UB, /LB Access Time
tBA
-
60
-
70
Chip Select to Low-Z Output
tLZ
10
-
10
-
Read
/UB, /LB Enable to Low-Z Output
tBLZ
10
-
10
-
Output Enable to Low-Z Output
tOLZ
5
-
5
-
Chip Disable to High- Z Output
tHZ
0
5
0
5
/UB, /LB Disable to High- Z Output
tBHZ
0
5
0
5
Output Disable to High- Z Output
tOHZ
0
5
0
5
Output Hold from Address Change
tOH
5
-
5
-
Write Cycle Time
tWC
60
40k
70
40k
Chip Select to End of Write
tCW
50
-
60
-
Address Set-up Time
tAS
0
-
0
-
Address Valid to End of Write
tAW
50
-
60
-
/UB, /LB Valid to End of Write
tBW
50
-
60
-
Write Write Pulse Width
tWP
50
-
50
-
Write Recovery Time
tWR
0
-
0
-
Write to Output High-Z
tWHZ
0
5
0
5
Data to Write Time Overlap
tDW
20
-
20
-
Data Hold from Write Time
End Write to Output Low-Z
tDH
0
-
0
-
tOW
5
-
5
-
Page Mode Cycle Time
tPC
25
-
25
-
Page Page Mode Address Access Time
tPAA
-
25
-
25
Maximum Cycle Time
tMRC
-
40k
-
40k
/CS High Pulse Width
tCP
10
-
10
-
1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
Revision 0.5
Jul. 2006