CMP1617BAX-E Datasheet, PDF (10/12 Pages) FIDELIX – 1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM

CMP1617BAx-E
CMOS LPRAM
LOW POWER MODES
1. Mode Register Set
A19 ~ A5
A4
A3
A2
A1
A0
0
ZZ
Enable/Disable
Array On/Off
on /ZZ
Half Selection
Array Refresh Area
/ZZ Enable/Disable
A4
Type
0
Deep Power Down Enable
1
DPD Disable (Default)
Note: If the register is written to enable the Deep
Power Down, the part will go into Deep Power Down
during the following time that /ZZ is driven low and
there is no MRS update. When /ZZ is driven high, all
of the register settings will return to default state for
the part (i.e. full array refresh, Deep Power Down
Disabled).
Half Selection (Top / Bottom)
A2
Type
0
Bottom (Default)
1
Top
Array On/Off on /ZZ
A3
Type
0
Partial Array Refresh Mode (Default)
1
Reduced Memory Size Mode
Note: The RMS(Reduced Memory Size) mode is enabled after
/ZZ goes high and remains enabled after /ZZ goes high. To
change to a different mode, the mode register will have to be
rewritten.
Array Refresh Area
A1 A0
0
0
0
1
1
0
1
1
Type
Full Array (Default)
RFU
½ Array
¼ Array
2. MRS Update
Address
/CS
/UB, /LB
/WE
/ZZ
tAS(3)
tZZWE
tWC
tCW(2)
tAW
tBW
tWP(1)
tWR(4)
Register Write Start
Register Write
Complete
Register Update
Complete
The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without any
updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a
don’t care When /ZZ is low during the register updates.
10
Revision 0.5
Jul. 2006