ISL9N322AD3ST Datasheet, PDF (9/11 Pages) Fairchild Semiconductor – N-Channel Logic Level UltraFET Trench MOSFET 30V, 20A, 0.022 Ω

SABER Electrical Model
REV January 20001
template isl9n322AD3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 1.28e-11, rs = 8.48e-3, trs1 = 1.6e-3, trs2 = 3e-6, xti=2, cjo = 5.7e-10, tt = 9.5e-9, m = 0.57)
dp..model dbreakmod = (rs = 0.22, trs1 = 8e-4, trs2 = -8.9e-6)
dp..model dplcapmod = (cjo = 3.7e-10, isl=10e-30, nl=10, m=0.48)
m..model mmedmod = (type=_n, vto = 1.99, kp=8, is=1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.4, kp = 32, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.62, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -3.0, voff = -2.0)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.0, voff = -3.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.5) DPLCAP ₅
c.ca n12 n8 = 8e-10
c.cb n15 n14 = 9e-10
c.cin n6 n8 = 8.9e-9
10
RSLC2
RSLC1
51
LDRAIN
DRAIN
2
RLDRAIN
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
-
ESG
6
8
50
RDRAIN
DBREAK
11
i.it n8 n17 = 1
LGATE
+
EVTEMP
EVTHRES
16
+ ₁₉ - ²¹
8
MWEAK
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 4.41e-9
l.lsource n3 n7 = 3.99e-9
GATE
1
RGATE _{+ 18 - 6}
9
20 ²²
RLGATE
MMED
MSTRO
EBREAK
+
17
18
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
CIN
8
-
7
DBODY
LSOURCE
SOURCE
3
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RSOURCE
RLSOURCE
res.rbreak n17 n18 = 1, tc1 = 9e-4, tc2 = 0
res.rdrain n50 n16 = 2e-3, tc1 = 2e-2, tc2 = 4e-5
S1A
12 ₁₃
8
S2A
14
15
13
RBREAK
17
18
res.rgate n9 n20 = 2.65
S1B
S2B
RVTEMP
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 44.1
res.rlsource n3 n7 = 39.9
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 = 1e-7
res.rslc2 n5 n50 = 1e3
CA
13
CB
+
+ ¹⁴
IT
EGS
6
8
EDS
5
8
-
-
8
19
-
VBAT
+
22
res.rsource n8 n7 = 1e-2, tc1 = 1e-3, tc2 =1e-6
RVTHRES
res.rvtemp n18 n19 = 1, tc1 = -2.6e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -1.6e-3, tc2 = -8e-6
spe.ebreak n11 n7 n17 n18 = 31.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/75))** 5))
}
}
©2002 Fairchild Semiconductor Corporation
Rev. B, January 2002