FMS3818 Datasheet, PDF(9/13 Page) Fairchild Semiconductor – Triple Video D/A Converter 3 x 8 bit, 180 Ms/s

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FMS3818 Datasheet, PDF (9/13 Pages) Fairchild Semiconductor – Triple Video D/A Converter 3 x 8 bit, 180 Ms/s

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PRODUCT SPECIFICATION

Timing Diagram

tPWL

tPWH

1/fS

CLK

PIXEL DATA

& CONTROLS

OUTPUT

DataN

DataN+1

50%

3%/FS

tSET

FMS3818

DataN+2

90%

10%

Applications Information

Figure 4 illustrates a typical FMS3818 interface

circuit. In this example, an optional 1.2 Volt bandgap

reference is connected to the VREF output, overriding the

internal voltage reference source.

Grounding

It is important that the FMS3818 power supply is

well-regulated and free of high-frequency noise. Careful

power supply decoupling will ensure the highest quality

video signals at the output of the circuit. The FMS3818 has

separate analog and digital circuits. To keep digital

system noise away from the D/A converter, it is recom-

mended that power supply voltages come from the system

analog power source and all ground connections (GND) be

made to the analog ground plane. Power supply pins should

be individually decoupled at the pin.

Printed Circuit Board Layout

Designing with high-performance mixed-signal circuits

demands printed circuits with ground planes. Overall system

performance is strongly inï¬uenced by the board layout.

Capacitive coupling from digital to analog circuits may

result in poor D/A conversion. Consider the following

suggestions when doing the layout:

1. Keep the critical analog traces (VREF, IREF, COMP,

IOS, IOR, IOG) as short as possible and as far as

possible from all digital signals. The FMS3818 should

be located near the board edge, close to the

analog output connectors.

2. The power plane for the FMS3818 should be

separate from that which supplies the digital circuitry.

A single power plane should be used for all of the VDD

pins. If the power supply for the FMS3818 is the same

as that of the system's digital circuitry, power to the

FMS3818 should be decoupled with 0.1ÂµF and 0.01ÂµF

capacitors and isolated with a ferrite bead.

3. The ground plane should be solid, not cross-hatched.

Connections to the ground plane should have very short

leads.

4. If the digital power supply has a dedicated power plane

layer, it should not be placed under the FMS3818, the

voltage reference, or the analog outputs. Capacitive cou-

pling of digital power supply noise from this layer to the

FMS3818 and its related analog circuitry can have an

adverse effect on performance.

5. CLK should be handled carefully. Jitter and noise on

this clock will degrade performance. Terminate the

clock line carefully to eliminate overshoot and ringing.

Improved Transition Times

Output shunt capacitance dominates slowing of output

transition times, whereas series inductance causes a small

amount of ringing that affects overshoot and settling time.

With a doubly terminated 75â¦ load, transition times can be

improved by matching the capacitive impedance output of

the FMS3818. Output capacitance can be matched with a

220 nH inductor in series with the 75â¦ source termination.

REV. 1.2.2 11/11/01

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