FMS3818 Datasheet, PDF (4/13 Pages) Fairchild Semiconductor – Triple Video D/A Converter 3 x 8 bit, 180 Ms/s

FMS3818
PRODUCT SPECIFICATION
Pin Descriptions
Pin
Name
Pin Number
Clock and Data Inputs
CLK
26
R7-0
G7-0
B7-0
Controls
SYNC
47-40
9-2
23-16
11
BLANK
10
Video Outputs
IOR
33
IOG
32
IOB
29
Value
CMOS
CMOS
CMOS
CMOS
0.700 Vp-p
Pin Function Description
Clock Input. Pixel data is registered on the rising edge of CLK. CLK
should be driven by a dedicated buffer to avoid reflection induced jitter,
overshoot, and undershoot.
Red, Green, and Blue Pixel Data Inputs. RGB digital inputs are
registered on the rising edge of CLK.
Sync Pulse Input. Bringing SYNC LOW, disables a current source which
superimposes a sync pulse on the IOG output. SYNC and pixel data are
registered on the rising edge of CLK. SYNC does not override any other
data and should be used only during the blanking interval. If sync pulses
are not required, SYNC should be connected to GND.
Blanking Input. When BLANK is LOW, pixel data inputs are ignored and
the D/A converter outputs are driven to the blanking level. BLANK is
registered on the rising edge of CLK.
Red, Green, and Blue Current Outputs. Current source outputs can
drive VESA VSIS, and RS-343A/SMPTE-170M compatible levels into
doubly-terminated 75 Ohm lines. Sync pulses can be added to the green
output. When SYNC is HIGH, the current added to IOG is:
Voltage Reference
VREF
35
RREF
36
IOS = 2.33 (VREF / RREF)
+1.25 V
348 Ω
Voltage Reference Input/Output. Internal 1.25V voltage reference is
available on this pin. An external +1.25 Volt reference may be applied to
this pin to override the internal reference. Decoupling VREF to GND with
a 0.1µF ceramic capacitor is required.
Current-set Resistor Node. Full-scale output current of each D/A
converter is determined by the value of the resistor connected between
RREF and GND. Nominal value of RREF is found from:
RREF = 5.31 (VREF/IFS)
where IFS is the full-scale output current (amps) from the
D/A converter (without sync). Sync is 0.439 IFS.
D/A full-scale current may also be calculated from:
IFS = VFS/RL
COMP
34
0.1 µF
Where VFS is the full-scale voltage level and RL is the total resistive load
(ohms) on each D/A converter.
Compensation Capacitor Node. A 0.1 µF ceramic capacitor must be
connected between COMP and VDD to stabilize internal bias circuitry.
4
REV. 1.2.2 11/11/01