FDP16AN08A0 Datasheet, PDF (9/11 Pages) Fairchild Semiconductor – N-Channel PowerTrench MOSFET 75V, 58A, 16mΩ

SABER Electrical Model
rev March 2002
template FDB16AN08A0 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.4e-11,nl=1.08,rs=3.3e-3,trs1=2.2e-3,trs2=2.5e-9,cjo=1.2e-9,m=5.6e-1,tt=1.3e-8,xti=3.9)
dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=5e-10,isl=10e-30,nl=10,m=0.52)
m..model mmedmod = (type=_n,vto=3.2,kp=4,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=3.85,kp=70,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.7,kp=0.06,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-1.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1,voff=.5)
DPLCAP
10
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=.5,voff=-1)
5
RSLC1
LDRAIN
RLDRAIN
c.ca n12 n8 = 10e-10
c.cb n15 n14 = 8e-10
c.cin n6 n8 = 1.7e-9
RSLC2
51
ISCL
DRAIN
2
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11
spe.eds n14 n8
n7
n5
n17 n18
n8 = 1
=
85.40
GATE
1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
-
LGATE
ESG
6
8
+
EVTHRES
+ ₁₉ -
EVTEMP
8
RGATE _{+ 18 - 6}
9
20 ²²
RLGATE
CIN
50
RDRAIN
16
21
DBREAK
11
MWEAK
MMED
MSTRO
8
EBREAK
+
17
18
-
7
DBODY
LSOURCE
SOURCE
3
i.it n8 n17 = 1
l.lgate n1 n9 = 5.96e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 5.75e-9
res.rlgate n1 n9 = 59.6
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 57.5
S1A
12 ₁₃
8
S2A
14
15
13
S1B
S2B
CA
13
CB
+
+ ¹⁴
EGS
6
8
-
EDS
5
8
-
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
RSOURCE
RLSOURCE
RBREAK
17
18
RVTEMP
19
IT
-
VBAT
+
8
22
RVTHRES
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=9e-4,tc2=-5e-7
res.rdrain n50 n16 = 3.3e-3, tc1=1.9e-2,tc2=4e-5
res.rgate n9 n20 = 3.31
res.rslc1 n5 n51 = 1e-6, tc1=1.5e-3,tc2=3e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 7e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.3e-5
res.rvtemp n18 n19 = 1, tc1=-2.7e-3,tc2=1e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/200))** 3))
}
}
©2002 Fairchild Semiconductor Corporation
FDP16AN08A0 / FDB16AN08A0 Rev. A1