FAN4803CP2 Datasheet, PDF (9/12 Pages) Fairchild Semiconductor – 8-Pin PFC and PWM Controller Combo

PRODUCT SPECIFICATION
FAN4803
V_CC OVP
VCC is assumed to be a voltage proportional to the PFC
output voltage, typically a bootstrap winding off the boost
inductor. The VCC OVP comparator senses when this volt-
age exceeds 16V, and terminates the PFC output drive while
disabling the VEAO current sink. Once the VEAO current
sink is disabled, the VEAO voltage will charge unabated,
except for a diode clamp to VCC, reducing the PFC pulse
width. Once the VCC rail has decreased to below 16.2V the
VEAO sink will be enabled, discharging external VEAO
compensation components until the steady state voltage is
reached. Given that 15V on VCC corresponds to 400V on
the PFC output, 16V on VCC corresponds to an OVP level of
426V.
Component Reduction
Components associated with the VRMS and IRMS pins of a
typical PFC controller such as the ML4824 have been elimi-
nated. The PFC power limit and bandwidth does vary with
line voltage. Double the power can be delivered from a 220
V AC line versus a 110 V AC line. Since this is a combina-
tion PFC/PWM, the power to the load is limited by the PWM
stage.
VISENSE
VC1 RAMP
GATE
DRIVE
OUTPUT
Figure 10. Typical Peak Current Mode Waveforms
VOUT = 400V
RP
VEAO
4
RCOMP
CZERO
CCOMP
35µA
R1
VC1
C1
30pF
5V
+
COMP
–
GATE
OUTPUT
3 ^ISENSE
–4
VI _SENSE
Figure 11. FAN4803 PFC Control
REV. 1.2.3 11/2/04
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