FAN4803CP2 Datasheet, PDF (6/12 Pages) Fairchild Semiconductor – 8-Pin PFC and PWM Controller Combo

FAN4803
PRODUCT SPECIFICATION
In the case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during the OFF time of the switch. Figure 3 shows a leading
edge control scheme.
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns OFF
and Switch 2 (SW2) turns ON at the same instant to mini-
mize the momentary “no-load” period, thus lowering ripple
voltage generated by the switching action. With such
synchronized switching, the ripple voltage of the first stage
is reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method, substantially
reducing dissipation in the high-voltage PFC capacitor.
Typical Applications
One Pin Error Amp
The FAN4803 utilizes a one pin voltage error amplifier in the
PFC section (VEAO). The error amplifier is in reality a cur-
rent sink which forces 35µA through the output program-
ming resistor. The nominal voltage at the VEAO pin is 5V.
The VEAO voltage range is 4 to 6V. For a 11.3MΩ resistor
chain to the boost output voltage and 5V steady state at the
VEAO, the boost output voltage would be 400V.
Programming Resistor Value
Equation 1 calculates the required programming resistor
value.
Rp = ^{VBOOST − VEAO} = ^{400V − 5.0V} = 11.3MΩ
I_PGM
35µA
(1)
PFC Voltage Loop Compensation
The voltage-loop bandwidth must be set to less than 120Hz
to limit the amount of line current harmonic distortion.
A typical crossover frequency is 30Hz. Equation 1, for
simplicity, assumes that the pole capacitor dominates
the error amplifier gain at the loop unity-gain frequency.
Equation 2 places a pole at the crossover frequency,
providing 45 degrees of phase margin. Equation 3 places a
zero one decade prior to the pole. Bode plots showing the
overall gain and phase are shown in Figures 5 and 6. Figure 4
displays a simplified model of the voltage loop.
C_COMP
=
Rp
× V _BOOST
×
Pin
∆VEAO ×
C_OUT
× (2
×π
× f)²
(2)
300W
C_COMP
=
11.3MΩ
×
400V
×
0.5V
×
220µF
×
(2
×
π
×
30Hz)²
C_COMP = _16nF
L1
I1
+
VIN
DC
SW2 I2 I3
I4
SW1
RL
C1
REF
+_–EAU3
VEAO
RAMP
OSC
CLK
+ ^CMP
– _U1
U4
DFF
RQ
D U2
Q
CLK
RAMP
VEAO
VSW1
TIME
TIME
Figure 3. Typical Leading Edge Control Scheme.
6
REV. 1.2.3 11/2/04