7004 Datasheet, PDF (9/12 Pages) Bourns Electronic Solutions – Network Interface Device

levels approaching 390 watts are theoretically possible. Paralleling FETs allows this number to
be increased. The output waveforms of the bridge design look the same as the push pull. The
FET drain voltages are depicted in Figure 11.
V_IN
+
C1
U1
PWM
Gate
Gate
GND
Isolation
Input 1
Input 2
GND
Gate 1
Source 1
Gate 2
Source 2
Q1
Q2
D1
T1
D2
Q3
Q4
L1
V_OUT
+
C2
RTN
Figure 10. The basic circuit design for a full-bridge regulator topology.
V_GS(Q1&Q4)
V_GS(Q2&Q3)
V_DS(Q1&Q4)
V_DS(Q2&Q3)
PWM'ED EDGE
-V_IN
Can vary from
0 to V_IN
-V_IN
Can vary from
0 to V_IN
V_IN
2
V_{SW2 0}
I_{SW2 0}
V_IN
V_SAT
I_PK
I_MIN
SW
1-4
SW
2-3
TIME
TIME
Figure 11. Voltage and current waveforms for the full-bridge regulator.
©2001 Fairchild Semiconductor Corporation
9
Rev. A, June 2001