FODM8071 Datasheet, PDF (8/13 Pages) Fairchild Semiconductor – 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity

Schematics
Pulse Gen.
t_f = tr = 5ns
Z_O = 50Ω
Input
Monitoring
Node
R_IN
V_CC
0.1µF _VO
Monitoring
Node
C_L = 15pF
Input
I_F = 5mA
50%
Output
90%
10%
t_PHL
t_f
t_PLH
t_r
90%
50%
10%
V_OL
Figure 12. Test Circuit for Propagation Delay Time, Rise Time and Fall Time
I_F
A
B
V_FF
GND
V_CM
Pulse Gen
0.1µF
Bypass
V_DD
Output
(Vo)
V_CM
V_OH
Switching Pos. (A), IF = 0
0.8 x V_DD
CM_H
V_OL
0.8V
Switching Pos. (B), IF = 5mA
CM_L
Figure 13. Test Circuit for Instantaneous Common Mode Rejection Voltage
©2008 Fairchild Semiconductor Corporation
FODM8071 Rev. 1.0.6
8
www.fairchildsemi.com