FMS3810 Datasheet, PDF (8/11 Pages) Fairchild Semiconductor – Triple Video D/A Converters 3 x 8 bit, 150 Ms/s

FMS3810/3815
Timing Diagram
t_PWL
t_PWH
1/f_S
CLK
PIXEL DATA
& CONTROLS
OUTPUT
t_S
t_H
DataN
DataN+1
t_D
50%
3%/FS
t_SET
PRODUCT SPECIFICATION
DataN+2
90%
t_F
t_R
10%
Applications Information
Figure 4 illustrates a typical FMS3810/3815 interface
circuit. In this example, an optional 1.2 Volt bandgap
reference is connected to the VREF output, overriding the
internal voltage reference source.
Grounding
It is important that the FMS3810/3815 power supply is
well-regulated and free of high-frequency noise. Careful
power supply decoupling will ensure the highest quality
video signals at the output of the circuit. The FMS3810/3815
has separate analog and digital circuits. To keep digital
system noise from the D/A converter, it is recommended that
power supply voltages (VDD) come from the system analog
power source and all ground connections (GND) be made to
the analog ground plane. Power supply pins should be
individually decoupled at the pin.
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly influenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor D/A conversion. Consider the following
suggestions when doing the layout:
1. Keep the critical analog traces (VREF, IREF, COMP,
IOS, IOR, IOG) as short as possible and as far as
possible from all digital signals. The FMS3810/3815
should be located near the board edge, close to the
analog output connectors.
2. The power plane for the FMS3810/3815 should be
separate from that which supplies the digital circuitry.
A single power plane should be used for all of the VDD
pins. If the power supply for the FMS3810/3815 is the
same as that of the system's digital circuitry, power to
the FMS3810/3815 should be decoupled with 0.1µF and
0.01µF capacitors and isolated with a ferrite bead.
3. The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
4. If the digital power supply has a dedicated power plane
layer, it should not be placed under the FMS3810/3815,
the voltage reference, or the analog outputs. Capacitive
coupling of digital power supply noise from this layer to
the FMS3810/3815 and its related analog circuitry can
have an adverse effect on performance.
5. CLK should be handled carefully. Jitter and noise on
this clock will degrade performance. Terminate the
clock line carefully to eliminate overshoot and ringing.
8
REV. 1.08 12/21/00