FMS3810 Datasheet, PDF (4/11 Pages) Fairchild Semiconductor – Triple Video D/A Converters 3 x 8 bit, 150 Ms/s

FMS3810/3815
PRODUCT SPECIFICATION
Pin Descriptions
Pin
Name
Pin Number
LQFP
Clock and Pixel I/O
CLK
26
R7-0
G7-0
B7-0
Controls
SYNC
47-40
9-2
23-16
11
BLANK
10
Video Outputs
IOR
33
IOG
32
IOB
29
Value
TTL
TTL
TTL
TTL
0.714 Vp-p
Pin Function Description
Clock Input. The clock input is TTL-compatible and all pixel data is
registered on the rising edge of CLK. It is recommended that CLK be
driven by a dedicated TTL buffer to avoid reflection induced jitter,
overshoot, and undershoot.
Red, Green, and Blue Pixel Inputs. TTL-compatible RGB digital inputs
are registered on the rising edge of CLK.
Sync Pulse Input. Bringing SYNC LOW, turns off a 40 IRE (7.62 mA)
current source which forms a sync pulse on any D/A converter output
connected to IOS. SYNC is registered on the rising edge of CLK along
with pixel data and has the same pipeline latency as BLANK and pixel
data. SYNC does not override any other data and should be used only
during the blanking interval. If the system does not require sync pulses,
SYNC and IOS should be connected to GND.
Blanking Input. When BLANK is LOW, pixel inputs are ignored and the
D/A converter outputs are driven to the blanking level. BLANK is
registered on the rising edge of CLK and has the same two-pipe latency
as SYNC and Data.
Red, Green, and Blue Current Outputs. Current source outputs can
drive RS-343A/SMPTE-170M compatible levels into doubly-terminated
75 Ohm lines. Sync pulses may be added to the green output.
When SYNC is HIGH, the current added to IOG is:
Voltage Reference
VREF
35
RREF
36
IOS = 3.64 (VREF / RREF)
+1.235 V
590 Ω
Voltage Reference Input/Output. Internal 1.235V voltage reference is
available on this pin. An external +1.235 Volt reference may be applied to
this pin to override the internal reference. Decoupling VREF to GND with
a 0.1µF ceramic capacitor is required.
Current-setting Resistor. Full-scale output current of each D/A
converter is determined by the value of the resistor connected between
RREF and GND. Nominal value of RREF is found from:
RREF = 9.1 (VREF/IFS)
where IFS is the full-scale (white) output current (amps) from the
D/A converter (without sync). Sync is 0.4 IFS.
D/A full-scale (white) current may also be calculated from:
IFS = VFS/RL
COMP
34
0.1 µF
Where VFS is the white voltage level and RL is the total resistive load
(ohms) on each D/A converter. VFS is the blank to full-scale voltage.
Compensation Capacitor. A 0.1 µF ceramic capacitor should be
connected between COMP and VDD to stabilize internal bias circuitry.
4
REV. 1.08 12/21/00