AN-6086 Datasheet, PDF (8/18 Pages) Fairchild Semiconductor – Design Consideration for Interleaved Boundary Conduction Mode PFC

AN-6086
POUT _TON
POUTMAX
TONMAX
When the resulting maximum power limit to obtain the
desired phase management threshold is too high compared
to the nominal output power, the maximum power limit
level can be reduced using clamping circuit on COMP pin,
as shown in Figure 15. The COMP pin voltage is clamped
at 3.3V and the resulting maximum power limit level is
reduced from 170% to 130% of nominal output power.
18% of POUTMAX (TONMAX)
13% of POUTMAX (TONMAX)
0.2 _{0.73 0.93}
VCOMP
4.3
Figure 13. VCOMP vs. On Time of Gate Drive Signal
FAN9611/12 determines the phase management according
to the COMP pin voltage (0.73V and 0.93V). Since the
COMP pin voltage is proportional to the output power, the
power levels for phase shedding and adding are given as
percentages of limited maximum power, as shown in
Figure 13. Thus, the maximum power limiting factor
affects the actual phase management thresholds as
percentages of nominal output power, as shown in Figure
14, which shows an example where the maximum power
limit is 170% of the nominal output power. In that case, the
actual phase management thresholds are 22% and 31% of
nominal output power, which can maximize the efficiency
at 20% of nominal load for 80-plus efficiency requirement.
In this way, the phase management thresholds can be
adjusted upward by adjusting the maximum on time
(through R_MOT).
# of phase
operating
2
1
13% 18%
50%
# of phase
operating
Output Power Normalized to POMAX
2
POMAX=1.7 PONOMINAL
1
22% 31% 50%
100%
Output Power Normalized to PONOMINAL
100%
170%
Figure 15. COMP Voltage Clamping Circuit and Phase
Management Threshold
After determining the limited maximum output power, the
boost inductor maximum flux density should be examined
to make sure that the inductor is not saturated during
overload condition. The maximum flux density of boost
inductor during overload condition is given by:
B_max
=
I _L,PK ⋅ K_MAX ⋅ L
A_e ⋅ N _BOOST
(20)
Figure 14. Phase Management Threshold
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.4 • 4/22/10
8
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