SPT7721 Datasheet, PDF (7/11 Pages) Fairchild Semiconductor – 8-BIT, 250 MSPS ADC WITH DEMUXED OUTPUTS

Figure 2 – Dual Mode Timing Diagram
Vin
/CLK
CLK
U6-Reset
/Reset
Reset
Port A
N-2
tap
N-1
2.5 _{CLK Cycles of Latency}
N
N+1
N+2
550ps
550ps
treset
ts
tpd1
INTERLEAVED DATA OUTPUT
N-5
Invalid Data
Port B
N-6
tpd2
Port A
N-7
N-4
tpd3
N-5
PARALLEL DATA OUTPUT
N-2
Invalid Data
Port B
N-6
N-4
N-2
tpd2
DCLKOUT
/DCLKOUT
Vin
/CLK
CLK
U6-Reset
/Reset
Reset
N-2
tap
Port A
N-6
Port B
N-5
tpd2
Port A
N-6
Port B
N-5
/DCLKOUT
DCLKOUT
N-1
N
2.5 _{CLK Cycles of Latency}
N+1
N+2
550ps
550ps
treset
ts
tpd1
INTERLEAVED DATA OUTPUT
N-4
Invalid Data
N-2
PARALLEL DATA OUTPUT
Invalid Data
N-2
tpd1
Data Output Possibilities w/o Reset
N+3
N+4
tpd1
tpd1
N-1
N+1
N
N-1
N
N+3
N+4
tpd1
tpd1
N-1
N+1
N
N-1
N
SPT7721
7
11/8/01