SPT7721 Datasheet, PDF (11/11 Pages) Fairchild Semiconductor – 8-BIT, 250 MSPS ADC WITH DEMUXED OUTPUTS

PIN ASSIGNMENTS
AGND
1
PD
2
CLK
3
CLK
4
RESET
5
RESET
6
OVDD
7
DGND
8
DA7 (MSB)
9
DA6
10
DA5
11
SPT7721
TOP VIEW
44L TQFP
33
AGND
32
DMODE1
31
DMODE2
30
OVDD
29
DGND
28
DCLKOUT
27
DCLKOUT
26
DB7 (MSB)
25
DB6
24
DB5
23
DB4
PIN FUNCTIONS
Pin Name
V_IN+
V_IN–
DA₀–DA₇
Description
Non-Inverted Analog Input; nominally 1 V_P-P;
100k pullup to V_CC and 100k pulldown to AGND,
internally
Inverted Analog Input; nominally 1 V_P-P; 100k
pullup to V_CC and 100k pulldown to AGND,
internally
Data output; Bank A. 3 V / 5 V LVCMOS
compatible.
DB₀–DB₇
DCLK_OUT
DCLK_OUT
CLK
CLK
RESET
RESET
DMODE_1,2
PD
V_CM
AV_CC
OV_DD
AGND
DGND
Data output; Bank B. 3 V / 5 V LVCMOS
compatible.
Non-Inverted data output clock. 3 V / 5 V
LVCMOS compatible.
Inverted data output clock. 3 V / 5 V LVCMOS
compatible.
Non-Inverted clock input pin; 100k pulldown to
AGND, internally
Inverted clock input pin; 17.5k pullup to V_CC and
7.5k pulldown to AGND, internally
RESET synchronizes the data sampling and data
output bank relationship when in Dual Channel
Mode (DMODE₁ = 0); 100k pulldown to AGND,
internally
Inverted RESET input pin; 17.5k pullup to V_CC
and 7.5k pulldown to AGND, internally
Internally:
100k pulldown to AGND on DMODE1
50k pullup to V_CC on DMODE2
Data Output Mode pins:
DMODE₁ = 0, DMODE₂ = 0: Parallel Dual
Channel Output
DMODE₁ = 0, DMODE₂ = 1: Interleaved Dual
Channel Output
DMODE₁ = 1, DMODE₂ = X: Single Channel
Data Output on Bank A (125 MSPS max)
Power Down pin; PD = 1 for power-down mode.
Outputs set to high impedance in power-down
mode; 100k pulldown to AGND, internally
2.5 V Common Mode Voltage Reference Output
+5 V Analog Supply
+3 V / +5 V Digital Output Supply
Analog Ground
Digital Ground
ORDERING INFORMATION
PART NUMBER
SPT7721SIT
TEMPERATURE RANGE
–40 to +85 °C
PACKAGE
44L TQFP
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR
USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR
THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
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© Copyright 2002 Fairchild Semiconductor Corporation
SPT7721
11
11/8/01