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| FODM8061_10 Datasheet, PDF (7/12 Pages) Fairchild Semiconductor – High Noise Immunity, 3.3V/5V, 10Mbit/sec Logic Gate Output (Open Collector) Optocoupler | |||
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Schematics
Pulse Gen.
IF
5MHz
tf = tr = 5ns
DC = 50%
Input
Monitoring
Mode
RM
0.1µF
Bypass
350â¦
VO Monitoring
CLNode
Input
(IF = 7.5mA)
50%
Output
tf
tPHL
tPLH
tr
90%
1.5V
10%
VOL
Figure 11. Test Circuit for Propagation Delay Time, Rise Time and Fall Time
IF
SW
RM
0.1µF
Bypass
VCC
350â¦
VO Monitoring
CL Node
VCM
Pulse Gen
VCM 90%
1kV
10%
tr
VO (IF = 0mA)
VO (IF = 7.5mA)
0V
tf
VOH
0.8 VCC
0.8V
VOL
Figure 12. Test Circuit for Instantaneous Common Mode Rejection Voltage
©2009 Fairchild Semiconductor Corporation
FODM8061 Rev. 1.0.3
7
www.fairchildsemi.com
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