FOD0721 Datasheet, PDF (7/12 Pages) Fairchild Semiconductor – High CMR, 25Mbit/sec Logic Gate Optocoupler

Typical Performance Curves (Continued)
Figure 7. Typical Rise and Fall Time vs. Ambient Temperature
6.00
Frequency = 6.25MHz
Duty Cycle = 50%
V = V = 5.0V
DD1
DD2
5.50
5.00
tr
4.50
tf
4.00
3.50
3.00
-40
-20
0
20
40
60
T_A - Ambient Temperature (°C)
80
100
Figure 9. Typical Pulse Width Distortion vs. Output Load Capacitance
(FOD0710)
1.6
Frequency = 6.25MHz
Duty Cycle = 50%
V = V = 5.0V
D D1
DD 2
1.4
1.2
1.0
0.8
0.6
15
20
25
30
35
40
45
50
55
C_L - Output Load Capacitance (pF)
Figure 11. Typical Pulse Width Distortion vs. Output Load Capacitance
(FOD0721/FOD0720)
1.4
Frequency = 12.5MHz
Duty Cycle = 50%
V = V = 5.0V
DD 1
DD 2
1.3
1.2
1.1
1.0
0.9
0.8
15
20
25
30
35
40
45
50
55
C_L - Output Load Capacitance (pF)
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
7
Figure 8. Typical Propogation Delay vs. Output Load Capacitance
(FOD0710)
28
Frequency = 6.25MHz
Duty Cycle = 50%
V = V = 5.0V
27
DD 1
DD2
26
25
t
PLH
24
t
PHL
23
22
21
15
20
25
30
35
40
45
50
55
C_L - Output Load Capacitance (pF)
Figure 10. Typical Propogation Delay vs. Output Load Capacitance
(FOD0721/FOD0720)
27
Frequency = 12.5MHz
Duty Cycle = 50%
V = V = 5.0V
DD1
D D2
26
25
t
PLH
24
23
t
PHL
22
21
15
20
25
30
35
40
45
50
55
C_L - Output Load Capacitance (pF)
Figure 12. Typical Rise and Fall Time vs. Output Load Capacitance
(FOD0710)
12
Frequency = 6.25MHz
Duty Cycle = 50%
V = V = 5.0V
DD1
DD2
10
tf
8
tr
6
4
2
15
20
25
30
35
40
45
50
55
C_L - Output Load Capacitance (pF)
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