FOD0721 Datasheet, PDF (11/12 Pages) Fairchild Semiconductor – High CMR, 25Mbit/sec Logic Gate Optocoupler

V_DD1 = 5V
1
0.1µF
2
0V–5V
3
Pulse width = 40ns
Duty Cycle = 50%
4
8
7
0.1µF
V_O
6
C_L
5
V_DD2 = 5V
Input
t_PLH
V_IN
t_PHL
5V
50%
Output
90%
V_OUT ^10%
t_R
V_OH
2.5V
V_OL
t_F
Figure 16. Test Circuit for Propogation Delay Time and Rise Time, Fall Time
1
0.1µF
SW
2
A
B
V_DD1 = 5V
3
4
+–
V_CM
8
7
0.1µF
V_DD2 = 5V
V_O
6
C_L
5
GND
V_OH
V_OL
1kV
V_CM
Switching Pos. (A) V_IN = 5V
0.8 x V_DD
0.8V
Switching Pos. (B) V_IN = 0V
CM_H
CM_L
Figure 17. Test Circuit for Instantaneous Common Mode Rejection Voltage
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
11
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