FMS6501 Datasheet, PDF (7/16 Pages) Fairchild Semiconductor – 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

I²C Interface
Operation
The I²C compatible interface conforms to the I²C spec for
Standard Mode. Individual addresses may be written. There
is no read capability. The interface consists of two lines.
These are a serial data line (SDA) and a serial clock line
(SCL). Both lines must be connected to a positive supply
through an external resistor. Data transfer may be initiated
only when the bus is not busy.
Bit Transfer
One data bit is transferred during each clock pulse. The data
on the SDA line must remain stable during the HIGH period of
the clock pulse. Changes in the data line during this time will
be interpreted as a control signal.
SCL
SDA
Data line
stable;
data valid
Change
of data
allowed
Figure 2: Bit Transfer
Start and Stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is
HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line, while the clock is HIGH is defined as the
stop condition (P).
SCL
S
P
SDA
START condition
STOP condition
Figure 3: Definition of START and STOP conditions.
FMS6501 Rev. 1A
7
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