FMS6501 Datasheet, PDF (4/16 Pages) Fairchild Semiconductor – 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

Digital Interface
The I²C compatible interface is used to program output enables, input to output routing, input clamp / bias and output gain. The I²C
address of the FMS6501 is 0x06 (0000 0110) with the ability to offset it to 0x86 (1000 0110) by tying the ADDR pin high.
Both data and address data of eight bits each are written to the FMS6501 I²C address to access all the control functions.
There are separate internal addresses for each output. Each output’s address includes bits to select an input channel, adjust the out-
put gain, and enable or disable the output amplifier. More than one output can select the same input channel for one-to-many routing.
When the outputs are disabled they are placed in a high-impedance state. This allows multiple FMS6501 devices to be paralleled to
create a larger switch matrix. Typical output power-up times will be less than 500ns.
The clamp / bias control bits are written to their own internal address since they should always remain the same regardless of signal
routing. They are set based on the input signal connected to the FMS6501.
All undefined addresses may be written without effect.
Output Control Register Contents and Defaults
Control Name
Enable
Gain
In
Width
1 bit
2 bits
5 bits
Type
Write
Write
Write
Default
0
0
0
Bit(s)
7
6:5
4:0
Description
Channel Enable: 1=Enable, 0=Power Down¹
Channel Gain: 00=6dB, 01=7dB, 10=8dB, 11=9dB
Input selected to drive this output: 00000=OFF²,
00001=IN1, 00010=IN2,..., 01100=IN12
Output Control Register MAP
Register
Name
Address Bit 7
OUT1
0x01
Enable
OUT2
0x02
Enable
OUT3
0x03
Enable
OUT4
0x04
Enable
OUT5
0x05
Enable
OUT6
0x06
Enable
OUT7
0x07
Enable
OUT8
0x08
Enable
OUT9
0x09
Enable
Bit 6
Gain1
Gain1
Gain1
Gain1
Gain1
Gain1
Gain1
Gain1
Gain1
Bit5
Gain0
Gain0
Gain0
Gain0
Gain0
Gain0
Gain0
Gain0
Gain0
Bit4³
In4
In4
In4
In4
In4
In4
In4
In4
In4
Bit3
In3
In3
In3
In3
In3
In3
In3
In3
In3
Bit2
In2
In2
In2
In2
In2
In2
In2
In2
In2
Bit1
In1
In1
In1
In1
In1
In1
In1
In1
In1
Bit0
In0
In0
In0
In0
In0
In0
In0
In0
In0
Clamp Control Register Contents and Defaults
Control Name Width
Clmp
1 bit
Type
Write
Default
0
Bit(s)
7:0
Description
Clamp / Bias selection: 1 = Clamp, 0 = Bias
Clamp Control Register Map
Register
Name
CLAMP1
CLAMP2
Address
0x1D
0x1E
Bit 7
Clmp8
Resv’d
Bit 6
Clmp7
Resv’d
Bit5
Clmp6
Resv’d
Bit4
Clmp5
Resv’d
Bit3
Clmp4
Clmp12
Bit2
Clmp3
Clmp11
Bit1
Clmp2
Clmp10
Bit0
Clmp1
Clmp9
Notes:
1. Power Down places the output in a high impedance state so multiple FMS6501 devices may be paralleled. Power
Down also de-selects any input routed to the specified output.
2. When all inputs are OFF, the amplifier input will be tied to approximately 150mV and the output will go to
approximately 300mV with the 6dB gain setting.
3. In4 is provided for forward compatibility and should always be written as ‘0’ in the FMS6501.
FMS6501 Rev. 1A
4
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