AN4107 Datasheet, PDF (7/14 Pages) Fairchild Semiconductor – Design of Power Factor Correction

APPLICATION NOTE
AN4107
Diode average current can be calculated by (21). The total
diode loss can be calculated by (22) and then a diode can be
selected considering diode thermal characteristic.
I_Davg = I_O(max)
P_Diode = V_fI_Davg
(21)
(22)
3-2. Control circuit design
1) Output voltage sensing resistor and feedback loop design
R₁ is determined by the maximum output over voltage,
∆V_ovp and R₂ is determined by (23).
R-----₁
R₂
=
-V----^O-----–----2----.-5-
2.5
,R₁
=
-^∆----V----^O----^V----^P-
40µA
,R₂
=
----2---.--5---R----¹----
V_O – 2.5
(23)
The feedback loop bandwidth must be narrower than 20Hz
for the PFC application. Therefore a capacitor is connected
between INV and EA_OUT to eliminate the 120Hz ripple
voltage by 40dB. The error amp compensation capacitor can
be calculated by (24). To improve the power factor, C_comp
must be increased than the calculated value. And to improve
the system response, C_comp must be lowered than the
calculated value.
C_comp
=
--------------------------1---------------------------
0.01 ⋅ 2π ⋅ 120Hz ⋅ R₁
(24)
2) Zero current detection resistor design
Idet current should be less than 3mA, therefore zero current
detection resistor is determined by (25).
R_idet
>
N-----_{a---u---x----}⋅_---V----O--
N_P ⋅ 3mA
3) Start-up circuit design
To start up the FAN7527, the start-up current must be
supplied through a start-up resistor. The resistor value is
calculated by (26) and (27). The start-up capacitor must
supply IC operating current before the auxiliary winding
supplies IC operating current maintaining Vcc voltage
higher than the UVLO voltage. Therefore the start up
capacitor is designed by (28).
R_ST
≤
V-----_{i--n---(-p---e---a--k---_--m----i-n---)---–----V-----t-h---(--s--t--)--m----a--x-}
I_STmax
( 26 )
P_Rst
=
V-----²_---i_-n_---(_--r_--m_----s_--__--m_----a_--x_---)
R_ST
≤
0.5W
( 27 )
C_ST
≥
---------------------I--^d--^c---^c--------------------
2π ⋅ f_ac ⋅ HY_(ST)min
( 28 )
4) Line voltage sense resistor and current sense resistor
design
The maximum line voltage sensing gain is determined by
(29) at the highest line.
V_PIN3
=
V _{i n ( p e a k _max )}
⋅
---------R----ⁱ--ⁿ---²---------
R_in1 + R_in2
= V_{in(peak_max)} ⋅ G_in(max) < 3.8V
( 29 )
Calculate the pin 3 voltage at the lowest line using G_in(max)
by (30). Then the current sense resistor is determined by
(31), (32) and (34). Once the current sense resistor is
determined, then the minimum line voltage sensing gain,
G_in(max) is determined by (31).
VO_(m)
=
K
⋅
V _{i n ( p e a k _min )}
⋅
----------R----i---n---2-----------
Rin1 + Rin2
∆
V
m
2
(m
a
x)
(30)
Rsemse
<
----------V-----O----⁽---m-----⁾----------
I _{L ( p e a k _max )}
=
K
⋅
Vi _{n ( p e a k _min )}
⋅
----------R----i--n----2-----------
Rin1 + Rin2
⋅ 2.5V ⋅ -^η--₄--V---_â‹-i-V-n----⁽_{O--p---I-e-O--a---(}^{k--m-_---m-a----xi--n-}₎--⁾-
(31)
Rsense
<
-------------1---.--8---V----------------
IL _{( p e a k _max )}
=
1.8
V
-^η----V----i--n----⁽--p----e---a---k---_---m-----i--n---⁾
4 ⋅ VOIO_(max)
( 32 )
PRsense
=
2
⋅



-_η----V--V--i--On----₍-I-p-O---e--⁽-a-m--k---_-a--m-x---⁾-i--n----_{)}
2
⋅
Rsense
<
1W
( 33 )
Rs
e
n
s
e
<
1----W----
2
⋅



-^η----V--V--i--On----⁽-I-p-O---e--₍-a-m--k---_-a--m-x---₎-i--n----^{)}
2
( 34 )
And attach 1nF capacitor in parallel with R2 to reduce the
switching ripple voltage.
4. Design Example
A 100W converter is designed to illustrate the design proce-
dure. The system parameters are as follows.
• Maximum output power : 100W
• Input voltage range : 85Vrms~265Vrms
• Output voltage : 400V
• AC line frequency : 60Hz
• PFC efficiency : 90%
• Minimum switching frequency : 34kHz
• Input displacement factor(IDF) : 0.98
• Input capacitor ripple voltage : 24V
• Output voltage ripple : 8V
• OVP set voltage : 450V
4-1. Inductor design
The boost inductor is determined by (6). Calculate it at both
the lowest line and the highest line and choose the lower
value. The calculated value is 586uH. To get the calculate
inductor value, EI3026 core is used and the primary winding
is 62 turns. The air gap is 0.586mm at both legs of the EI
core. The auxiliary winding is determined by (7) and the
auxiliary winding is 5 turns.
4-2. Input capacitor design
The minimum input capacitance is determined by the input
voltage ripple specification. The calculated minimum input
©2001 Fairchild Semiconductor Corporation
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