AN-7820 Datasheet, PDF (7/17 Pages) Fairchild Semiconductor – EVALUATION BOARD

Table 6 : Critical Timing Specifications
Parameter Description
Min Typ Max Unit
tHTS THA, Hold to Track
Settling Time
X
X
X
tTHS THA, Track to Hold
Settling Time
X
X
X
tacq
SPT7820 ADC
Acquisition Time
4 V Step
20
nsec
tacq
SPT7824 ADC
Acquisition Time
4 V Step
12
nsec
th1
Hold Time After the
ADC Rising Clock
5
nsec
X= This Limit Depends on the THA Chosen
The settling time to 1/2 LSB (1.953 mV) is one of the principal
requirement in a 10-bit THA. This includes both track to hold
(tTHS) and hold-to-track (tHTS) settling time. tHTS varies
with the step size (voltages) that the THA needs to swing. The
rising edge of the ADC’s clock should be placed after tTHS
has settled. SPT7820/24 requires that the analog input be
held for an additional 5 nsec minimum (th1) after the rising
edge of the clock. Figure 9 shows the ADC running at
Nyquist; the sampling frequency is practically twice the input
frequency. In this example, the ADC could have as much as
a 4 Volt step (±FS) from one conversion to the next. The
acquisition time (tacq) of the ADC must be met. This is the
time necessary to allow the internal THA of the SPT7820/24
to track (CLK= low) and settle to 1/2 LSB while the input is
sharply changed to its new continuous level. The minimum
acquisition time is 20 nsec for a 4 volt step and 12 nsec for a
0.5 volt or less step.
The maximum sampling rate of the SPT7820 or SPT7824
when driving from an external THA can be decided from the
proper combination of tTHS, tHTS and tacq .
The pedestal and the droop of the THA shown in figure 9 are
not critical to the dynamic performance as long as they are
constant with respect to the analog input range. They are
seen as offset errors.
LOW LEVEL ANALOG INPUT SIGNAL
SPT7820 and SPT7824 require that the analog input (VIN)
range be operated within ± 2 V ± 2%. Amplification and level
shifting are needed for a low voltage level VIN.
Figure 10: Driving Circuit Block Diagram
VIN
AMP1
THA
AMP2
SPT7820/24
Figure 10 shows the typical analog driving circuit. AMP1 and/
or AMP2 are optional. For an application in which noise is the
major concern, use AMP1 (disregard AMP2) low noise ampli-
fier to gain up to ± 2 volts before getting to the THA. In another
application in which high frequency VIN is the major concern,
use AMP2 instead of AMP1 to amplify the THA signal to ±2
volts before reaching to SPT7820 or SPT7824. In the latter
case, the low level VIN provides a faster acquisition time for
the THA.
UNCOMMITTED PROTO SOCKET SPACE
Referring to the detail schematic figure 17, there are two slots
available for applications where additional circuits may be
needed to interface with the EB7820/24. These two slots
(labeled A and D in the PCB assembly) are electrically
noncommitted:
- Slot A is physically located near VIN (BNC) and is in-
tended for the analog interfacing circuit. It has one 16-
DIP and one 8-SIP.
- Slot D is physically located between P2 and P3 connectors
and is intended for the digital interfacing circuit. It has
three 16-DIPs, three 8-SIPs and one 37-pin D connector.
Both slots have the appropriate power supplies and
grounds in their vicinity as labeled.
DB792 DAUGHTER BOARD (RECONSTRUCTION DAC)
DB792 (figure 18) is the daughter board that interfaces directly
to the EB7820/24 via P2 and P3. It is suited for an application
where the reconstruction DAC is needed to evaluate the ADC
performance in the time domain. DB792 is designed around
the Analog Device's AD9713, 12-bit TTL, digital-to-analog
converter, 80 MSPS update rate. It is setup in bipolar
operation. The detailed schematic is shown in figure 18.
Refer to Analog Device's AD9713B data sheet for detail.
SPT7820/24 INPUT AND LATCH-UP PROTECTIONS
The SPT7820/24 is free from any possible latch-up when the
recommended interfacing circuit as shown in figure 11 is
followed. The following lists are for both latch-up and input
protection interface requirements:
1) Drive the input clock (pin 15) from a TTL logic (VIH ≤ 4.5
V). Fast TTL logic family or equivalent is strongly recom-
mended due to its fast rise time (6 nsec or faster). In the
event in which the clock is driven from a high current
source (greater than 400 mA), use a 100 Ω resistor in
series to current limit to roughly 45 mA.
2) D1 is a Schottkey or hot carrier diode (Motorola, 1N5817
or eq.) installed between VEE and AGND (reverse bias).
3) Both VCC (pin 18 & 25) and DVCC (pin 14 and 28) are
driven from the same analog +5 V supply.
4) Mount the ferrite beads (FB1 and FB2) as closely to the
device as possible. The bead to ADC connections should
not be shared with any other device.
AN7820/24
7
5/22/97