AN-7820 Datasheet, PDF (4/17 Pages) Fairchild Semiconductor – EVALUATION BOARD

SPT7824 and 20 to 300 nsec for SPT7820. This is due to the
internal THA. When operating the SPT7820 or SPT7824
faster than 3 MSPS, keep the clock duty cycle at approxi-
mately 50% ±10%. The probe jack PJ1 is the monitoring test
point for the CLK IN. Use this test point when adjusting the
clock duty cycle.
Logic low of the CLK IN (pin 17) causes the internal THA to
go into track. It is necessary to keep the SPT7820 or
SPT7824 in the track mode when the device is idle for an
extended period of time or at the start-up time. This setup will
prevent the internal THA from going to saturation due to the
internal THA’s droop. EB7820/24 provides a logic low to the
clock of the SPT7820/24 when the pulse generator (CLK) is
removed from the evaluation board.
TTL-OUTPUT DATA LATCHES
The rise time (Trise) and fall time (Tfall) of SPT7820/24 (D0-
D9) are not symmetrical. The propagation delay with respect
to trise (at the 2.4 V crossing) is typically 14 nsec and 6 nsec
is typical with respect to tfall (at the 2.4 V crossing). Figure
5 shows the actual output characteristic of the SPT7820/24.
This nonsymmetrical trise and tfall creates approximately
8 nsec of invalid data.
In an application where a reconstruction DAC is needed, the
above invalid data zone will cause the reconstruction signal
to have an unwanted heavy glitch if the DAC is directly
interfaced with SPT7820 or SPT7824. To avoid this, buffer
the SPT7820/24 by the edge-triggered latches. FAST family
TTL logic will fit well in this application due to its fast setup and
hold time.
U7 and U8 (74F174) are the output latches. The FAST family
TTL-logic is very sensitive to electrostatic discharge (ESD).
RN1 and RN2 are the 8 pin SIP resistor networks, 10 kΩ.
They protect U7 and U8 by providing the ESD path to DGND.
The BNC connector (CCLK) is the capture clock, which has
51 Ω termination R12 on board. The outputs of the data
latches (D0-D9) are routed through the standard 26-pin
female ribbon connector (P2). SJ3-5 are the solder jumper
options for the capture clock. Only one of these jumpers
needs to be connected:
- When SJ3 is installed (factory installed when this board is
shipped), SPT7820/24 and the latches (U7 and U8) are
clocked at the same time. With this configuration, the data
seen at the connector P2 adds another clock of latency
(two clocks of latency total as shown in figure 6).
- When SJ4 is installed, the capture clock must be supplied
externally through CCLK. The setup time (ts) and hold
time (th) in table 5 must be met when selecting this option.
- When SJ5 is selected, the buffers will be latched at the
falling edge of the CLK IN (SPT7820/24). With this option,
the setup time (ts) and hold time requirements for the
74F174 latches must be met (table 5). The placement of
this capture clock edge is dependent on the clock pulse
width and the sampling frequency. This option is not
recommended above 25 MSPS to avoid latching the
invalid data.
Figure 5 - Digital Output Characteristic of the SPT7820 or SPT7824
N
N+1
CLK IN
2.4V
3.5V
DATA OUT 2.4V
(Actual)
0.8V
0.5V
DATA OUT
(Equivalent)
6nS
typ.
(N-2)
Invalid
Data
tpd1
(14 nS typ.)
(N-2)
INVALID
DATA
(N-1)
(N-1)
Rise Time
≤ 6nSEC
Invalid
Data
(N)
INVALID
DATA
(N-1)
The digital outputs (latched) are routed through P2, 26 pin ribbon connector. (See table 4.)
The overrange bit (D10) could be viewed through test point TP13. D10 does not bring out through P2.
AN7820/24
4
5/22/97