SSTV16859 Datasheet, PDF (6/8 Pages) Fairchild Semiconductor – Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset

AC Loading and Waveforms (See Notes A through F below)
Note: C_L includes probe and jog capacitance
FIGURE 1. AC Test Circuit
FIGURE 2. Voltage Waveforms - Pulse Duration
Note: I_DD tested with clock and data inputs held at V_DD or GND,
and I_O = 0 mA.
FIGURE 3. Voltage and Current Waveforms Inputs
Active and Inactive Times
FIGURE 4. Voltage Waveforms -
Propagation Delay Times
FIGURE 5. Voltage Waveforms - Setup and Hold Times
FIGURE 7. Voltage Waveforms -
RESET Removal Delay Times
FIGURE 6. Voltage Waveforms -
RESET Propagation Delay Times
Note A: All input pulses are supplied by generators having
the following characteristics:
PRR ≤ 10 MHz, Z₀ = 50Ω, input slew rate = 1V/ns ± 20%
(unless otherwise specified).
Note B: The outputs are measured one at a time with one
transition per measurement.
Note C: V_TT = V_REF = V_DD/2.
Note D: V_IH = V_REF +310 mV (AC voltage levels) for differ-
ential inputs. V_IH = V_DD for LVCMOS input.
Note E: V_IL = V_REF −310 mV (AC voltage levels) for differ-
ential inputs. V_IL = GND for LVCMOS input.
Note F: Removal time (t_REM) is tested with one data input
held active HIGH. The propagation time from CK to the cor-
responding output must meet valid timing specifications for
the measurement to be accurate.
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