SSTV16859 Datasheet, PDF(1/8 Page) Fairchild Semiconductor – Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset

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SSTV16859 Datasheet, PDF (1/8 Pages) Fairchild Semiconductor – Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset

March 2001

Revised July 2002

SSTV16859

Dual Output 13-Bit Register with

SSTL-2 Compatible I/O and Reset

General Description

The SSTV16859 is a dual output 13-bit register designed

for use with 184 and 232 pin DDR-1 memory modules. The

device has a differential input clock, SSTL-2 compatible

data inputs and a LVCMOS compatible RESET input. The

device has been designed to meet the JEDEC DDR mod-

ule register specifications.

The device has been fabricated on an advanced sub-

micron CMOS process and is designed to operate at power

supplies of less than 3.6Vâs.

Features

I Compliant with DDR-I registered module specifications

I Operates at 2.5V Â± 0.2V VDD

I SSTL-2 compatible input structure

I SSTL-2 compliant output structure

I Differential SSTL-2 compatible clock inputs

I Low power mode when device is reset

I Industry standard 64 pin TSSOP package

I Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Ordering Code:

Order Number Package Number

Package Description

SSTV16859G

(Note 1)(Note 2)

BGA96A

96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

SSTV16859MTD

(Note 2)

MTD64

64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Note 1: Ordering code âGâ indicates Trays.

Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter âXâ to the ordering code.

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