FMS6243 Datasheet, PDF (6/10 Pages) Fairchild Semiconductor – Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control

The same circuits can be used with AC-coupled outputs
if desired. Here is the DC-coupled input with an AC-cou-
pled output.
DVD or
STB
SoC
DAC
Output
0V - 1.4V
LCVF
75Ω
Clamp
Inactive
Figure 9. DC-Coupled Inputs, AC-Coupled Outputs
External video
source must
be AC coupled
0V - 1.4V
0.1μ
75Ω
LCVF
Clamp
Active
75Ω ^220μ
Figure 10. AC-coupled Inputs and Outputs
External video
source must
7.5MΩ
be AC coupled ^0.1μ
LCVF
75Ω
Bias
Input
75Ω
500mV +/-350mV
Figure 11. Biased AC-Coupled Inputs with
AC-Coupled Outputs
NOTE: The video tilt or line time distortion is dominated
by the AC-coupling capacitor. The value may need to be
increased beyond 220µF to obtain satisfactory operation
in some applications.
where:
V_O = 2V_in + 0.280V
I_CH = (I_CC / 3) + (V_O/R_L)
V_IN = RMS value of input signal
I_CC = 24mA
V_s = 5V
R_L = channel load resistance
Board layout can also affect thermal characteristics.
Refer to the Layout Considerations section for more
information.
The FMS6243 is specified to operate with output cur-
rents typically less than 50mA, more than sufficient for a
dual (75Ω) video load. Internal amplifiers are current lim-
ited to a maximum of 100mA and should withstand brief-
duration, short-circuit conditions; however, this capability
is not guaranteed.
Group Delay Adjustment
The FMS6243 has the ability to independently adjust
each channel for Sin X/X group delay and Chroma/Luma
delay. This is accomplished by placing a capacitor from
the device delay adjust pin to ground. The group delay
can be adjusted from the nominal of +10ns to -80ns. This
means that, under a nominal situation, a video system
may have an overall group delay measurement of
+50ns. If the system specification is +40ns, the
FMS6243 could be used to decrease this group delay to
fall well within specification with a guard band to allow for
system variation.
Adding a 50pF capacitor to the desired channel DCap
pin (see Figure 15) generates a -20ns delay through the
FMS6243, which, when summed with the +50ns of the
system, gives a new system overall group delay of
+30ns. It now meets the system specification with a
+10ns guard band for system group delay variation.
Figure 12 shows the effect on group delay by adding
capacitance to the FMS6243 DCap pins. The correct
capacitor can be chosen by determining the format of the
video system (NTSC 3.58 or PAL 4.43), then choosing
the desired group delay to sum with overall system
delay. The desired delay and format line intersection is
the delay capacitor needed for the DCap pins.
Power Dissipation
The output drive configuration must be considered when
calculating overall power dissipation. Care must be taken
not to exceed the maximum die junction temperature.
The following example can be used to calculate power
dissipation and internal temperature rise:
T_j = T_A + P_d • Θ_JA
where:
P_d = P_CH1 + P_CH2 + P_CH3
and P_CHx = V_s • I_CH - (V_O2/R_L)
40
400kHz Ref
20
0
-20
-40
-60
-80
3.58MHz
4.43MHz
10pF
20pF
30pF
40pF
50pF
60pF
70pF
80pF
-100
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Frequency (MHz)
Figure 12. Group Delay vs. Delay Cap. Value
© 2007 Fairchild Semiconductor Corporation
FMS6243 Rev. 1.0.0
6
www.fairchildsemi.com