FDMC612PZ Datasheet, PDF (6/7 Pages) Fairchild Semiconductor – P-Channel PowerTrench® MOSFET

Dimensional Outline and Pad Layout
0.10 C
A
“
2X
B
“
PIN1
IDENT
TOP VIEW
0.10 C
2X
0.45(4X)
(3.40)
2.37
8
5
2.15
(1.70)
(0.40)
(0.65)
1
0.65
1.95
KEEP OUT
AREA
0.70(4X)
4
0.42(8X)
A _0.8MAX
0.10 C
ƒ0$;
(0.20)
0.08 C
0.05
0.00
SEATING
PLANE
1
0.45+0.05
(4X)
(1.20)
0.45+0.05
(3X)
8
0.65
SIDE VIEW
C
2.27+0.05
4
(0.40)
2.05+0.05
A
5
0.32+0.05 (8X)
RECOMMENDED LAND PATTERN
NOTES:
A.EXCEPT AS NOTED, PACKAGE CONFORMS TO
JEDEC REGISTRATION MO-240 VARIATION BA..
B.DIMENSIONS ARE IN MILLIMETERS.
C.DIMENSIONS AND TOLERANCES PER
ASME Y14.5M,1994.
D.SEATING PLANE IS DEFINED BY TERMINAL TIPS ONLY
E.BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH
PROTRUSIONS NOR GATEBURRS.
F.FLANGE DIMENSIONS INCLUDE INTERTERMINAL FLASH
OR PROTRUSION. INTERTERMINAL FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25MM PER SIDE.
G.IT IS RECOMMENDED TO HAVE NO TRACES OR VIA
WITHIN THE KEEP OUT AREA.
H.DRAWING FILENAME: MKT-MLP08Trev3.
I.GENERAL RADII FOR ALL CORNERS SHALL BE 0.20MM
MAX.
J.FAIRCHILD SEMICONDUCTOR.
1.95
0.10 C A B
0.05 C
BOTTOM VIEW
©2013 Fairchild Semiconductor Corporation
6
FDMC612PZ Rev.C3
www.fairchildsemi.com