FAN2013 Datasheet, PDF (6/9 Pages) Fairchild Semiconductor – 2A Low-Voltage Current-Mode Synchronous PWM Buck Regulator

Block Diagram
PG
V_IN
PV_IN
REF
PG
COMP
FB
DIGITAL
SOFT START
FB
ERROR
AMP
0.8V
COMP
GND
UNDER VOLTAGE
LOCKOUT
IS
CURRENT
SENSE
LOGIC
MOSFET
SW
CONTROL
DRIVER
GND
IS
OSC
SLOPE COMPENSATION
OVER
VOLTAGE
COMP
REF FB
GND
Figure 10. Block Diagram
Operation Description
The FAN2013 is a step-down pulse-width modulated
(PWM) current mode converter with a fixed switching fre-
quency of 1.3MHz. At the rising edge of each clock
cycle, the P-channel transistor is turned on until the
PWM comparator trips or the current limit is reached.
During the ON time, the inductor current ramps up and is
monitored by the internal current-mode control loop.
After a minimum dead time, the N-channel transistor is
turned ON and the inductor current ramps down. As the
clock cycle is completed, the N-channel switch is turned
OFF and the next clock cycle starts. The duty cycle is
given by the ratio of output voltage and input voltage.
The converter runs at minimum duty cycle when output
voltage is at minimum and input voltage is at maximum,
and at 100% duty cycle when the input voltage
approaches the output voltage, as described below.
100% Duty Cycle Operation
As the input voltage approaches the output voltage and
the duty cycle exceeds the typical 95%, the converter
turns the P-channel transistor continuously on. In this
mode, the output voltage is equal to the input voltage,
minus the voltage drop across the P-channel transistor:
V_OUT = V_IN – I_LOAD × (R_{DS_ON} + R_L)
where
EQ 1
R_{DS_ON} = P-channel switch ON resistance
I_LOAD = Output current
R_L = Inductor DC resistance
UVLO and Soft Start
The internal voltage reference, V_REF, and the IC remain
reset until V_IN reaches the 3.7V UVLO threshold.
The FAN2013 has an internal soft-start circuit that limits
the in-rush current during start-up. This prevents possi-
ble voltage drops of the input voltage and eliminates the
output voltage overshoot. The soft-start is implemented
as a digital circuit, increasing the switch current in four
steps to the P-channel current limit (3.5A). Typical start-
up time for a 40µF output capacitor with a load current of
2.0A is 800µs.
Output Over-Voltage Protection
When output voltage, V_OUT, reaches approximately 7%
above the nominal value, the device turns OFF the P-
channel switch and turns ON part of the N-channel tran-
sistor with a built-in current limit of about 400mA. When
V_OUT reaches the hysteresis of about 2%, the device
starts switching normally in closed loop. If output voltage
is pulled up by an external voltage source with a current
limit higher than typical 400mA, the output voltage stays
up at the external voltage source level.
The over-voltage protection is designed to limit the out-
put voltage excursion in case of a transient response
from full load to a minimum load.
Output Short-Circuit Protection
The switch peak current is limited cycle by cycle to a typ-
ical value of 3.5A. In the event of an output voltage short
circuit, the device operates with a frequency of 400kHz
and minimum duty cycle, making the average typical
input current .45A.
Thermal Shutdown
When the die temperature exceeds 150°C, a reset
occurs and remains in effect until the die cools to 130°C,
when the circuit is allowed to restart.
© 2006 Fairchild Semiconductor Corporation
FAN2013 Rev. 1.0.0
6
www.fairchildsemi.com