AN-6208 Datasheet, PDF (6/10 Pages) Fairchild Semiconductor – Secondary-Side Synchronous Rectifier (SR) for LLC Resonant Converter

AN-6208
Printed Circuit Board Layout
In Figure 18, the power traces are marked as bold lines.
Good PCB layout improves power system efficiency and
reliability and minimizes EMI.
Guidelines
For feedback detection, the FD pin should be connected
to the anode of the opto diode. Connecting the FD pin
through a resistor can improve surge immunity of the
system. Keep trace 1 away from any power trace with
high pulsating current.
The control ground (trace 2) and power ground (trace 7)
should meet at a single point to minimize interference.
The connecting trace should be as short as possible.
APPLICATION NOTE
As indicated by 4, the ground of the feedback loop
should be connected to the negative terminal of
output capacitor C_O.
Trace 5 should be long and far from V_o terminal.
Keep trace 6 as short as possible.
As indicated by 7, the source terminals of Q₁ and Q₂
are connected to the negative terminal of C_o. Keep
trace 10 short, direct, and wide.
As indicated by 8, the negative terminal of C_o should
be connected to the case directly.
Figure 18.Layout Considerations
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 3/10/11
6
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