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74ABT573_07 Datasheet, PDF (6/13 Pages) Fairchild Semiconductor – Octal D-Type Latch with 3-STATE Outputs
AC Operating Requirements
SOIC and SSOP package.
Symbol
Parameter
fTOGGLE
tS(H)
tS(L)
tH(H)
tH(L)
tW(H)
Max Toggle Frequency
Set Time, HIGH or LOW Dn
to LE
Hold Time, HIGH or LOW Dn
to LE
Pulse Width, LE HIGH
TA = +25°C,
VCC = +5.0V,
CL = 50pF
Min. Typ. Max.
100
1.5
1.5
1.0
1.0
3.0
TA = –40°C to +85°C,
VCC = 4.5V to 5.5V,
CL = 50pF
Min.
Max.
1.5
1.5
1.0
1.0
3.0
Units
MHz
ns
ns
ns
Extended AC Electrical Characteristics
SOIC package.
Symbol
Parameter
TA = –40°C to +85°C,
VCC = 4.5V to 5.5V,
CL = 50pF,
8 Outputs
Switching(8)
Min.
Max.
TA = –40°C to +85°C,
VCC =
CL
4.5V to 5.5V,
= 250pF(9)
Min.
Max.
TA = –40°C to +85°C,
VCC = 4.5V to 5.5V,
CL = 250pF,
8 Outputs
Switching(10)
Min.
Max.
Units
tPLH Propagation Delay,
1.5
5.2
2.0
6.8
2.0
9.0
ns
tPHL Dn to On
1.5
5.2
2.0
6.8
2.0
9.0
tPLH Propagation Delay,
1.5
5.5
2.0
7.5
2.0
9.5
ns
tPHL LE to On
1.5
5.5
2.0
7.5
2.0
9.5
tPZH
tPZL
Output Enable
Time
1.5
6.2
2.0
8.0
2.0
10.5
ns
1.5
6.2
2.0
8.0
2.0
10.5
tPHZ Output Disable
1.0
5.5
(11)
tPLZ Time
1.0
5.5
(11)
ns
Notes:
8. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
9. This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors
in place of the 50pF load capacitors in the standard AC load. This specification pertains to single output switching
only.
10. This specification is guaranteed but not tested. The limits represent propagation delays for all paths described
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50pF load
capacitors in the standard AC load.
11. The 3-STATE delay times are dominated by the RC network (500Ω, 250pF) on the output and has been excluded
from the datasheet.
©1993 Fairchild Semiconductor Corporation
74ABT573 Rev. 1.4
6
www.fairchildsemi.com