RV4141A_05 Datasheet, PDF (5/7 Pages) Fairchild Semiconductor – Low Power Ground Fault Interrupter

RV4141A
PRODUCT SPECIFICATION
RSET is 1 MΩ, RSEC is 45Ω and the VOS of the sense ampli-
fier is its maximum of 200 µV, the trip current error is
±5.6%.
minimum delay time required to prevent nuisance tripping.
This will typically be 1 to 2 ms. The value of C2 required to
provide the desired delay time is:
The SCR anode is directly connected to a solenoid or relay
coil. It can be tripped only when its anode is more positive
than its cathode. It must have a high dV/dt rating to ensure
that line noise (generated by electrically noisy appliances)
does not falsely trigger it. Also the SCR must have a gate
drive requirement less than 200 µA. C3 is a noise filter that
prevents high frequency line pulses from triggering the SCR.
The relay solenoid used should have a response time of 3 ms
or less to meet the UL 943 timing requirement.
Sense Transformers and Cores
The sense and ground/neutral transformer cores are usually
fabricated using high permeability laminated steel rings.
Their single turn primary is created by passing the line and
neutral wires through the center of its core. The secondary is
usually from 200 to 1500 turns.
Transformers may be obtained form Magnetic Metals, Inc.
(www.magmet.com)
Calculating the Values of R_SET and C2
Determine the nominal ground fault trip current requirement.
This will be typically 5 mA in North America (117V AC)
and 22 mA in the UK and Europe (220V AC). Determine the
C2 = 6 x T
where:
C2 is in nF
T is the desired delay time in ms.
The value of RSET to meet the nominal ground fault trip cur-
rent specification is:
R_SET
=
-----------------------4---.--6----^×-----N--------------------------
I_FAULT × COS 180(T ⁄ P)
where:
RSET is in kΩ
T is the time delay in ms
P is the period of the line frequency in ms
IFAULT is the desired ground fault trip current in mA RMS
N is the number of sense transformer secondary turns.
This formula assumes an ideal sense transformer is used.
The calculated value of RSET may have to be changed up to
30% to when using a non-ideal transformer.
RTEST
Press to
Mov _{Sense Transformer}
1:1000
5 Ring Steel Core
15K
Test
Grounded Neutral
1:200
Phase
Line
Neutral
Normally Closed
Latching Contacts
Load
GFCI
C4
R _IN
470
C1
10 nF
R _SET
1
1.1 Meg
2
3
4
1000 pF
RV4141A
C2
8
12 nF
7
6
C
+
F
1µF 35V
5
Solenoid
R_N
R_B
0.4
20K
Q1
TAG
X0103DA
C3
10 nF
1N4004
R _LINE
24K
1W
R_G
1.6
Fault
Resistance
Not Part of
Application
Note:
1. Portions of this schematic are subject to U.S. patents 3,878,435 and Re. 30,678.
Figure 1. GFI Application Circuit
65-4141A-03
REV. 1.0.6 6/30/05
5