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GTLP6C816A Datasheet, PDF (5/7 Pages) Fairchild Semiconductor – LVTTL-to-GTLP Clock Driver
AC Electrical Characteristics
Over recommended range of supply voltage and operating free air temperature. VREF = 1.0V (unless otherwise noted).
CL = 30 pF for OBn-Port and CL = 50 pF for OAn-Port.
Symbol
From (Input)
To (Output)
Min
Typ
(Note 6)
Max
fTOGGLE
TTLIN
GTLPIN
OBn
175
OAn
175
tPLH
tPHL
TTLIN
OBn
1.3
2.3
4.0
0.9
2.6
4.3
tPLH
tPHL
tRISE
tFALL
tRISE
tFALL
OEB
OBn
Transition Time, OB Outputs (20% to 80%)
Transition Time, OB outputs (20% to 80%)
Transition Time, OA outputs (10% to 90%)
Transition Time, OA outputs (10% to 90%)
1.5
2.6
4.1
1.2
2.5
4.1
1.3
1.3
1.2
2.0
tPZH, tPZL
OEA
tPLZ, tPHZ
tPLH
GTLPIN
tPHL
Note 6: All typical values are at VCC = 3.3 V and TA = 25°C.
OAn
OAn
0.5
2.9
4.8
0.5
2.4
4.4
1.9
3.6
5.7
2.1
3.5
5.3
Units
MHz
ns
ns
ns
ns
ns
ns
Extended Electrical Characteristics
Over recommended ranges of supply voltage and operating free-air temperature VREF = 1.0V (unless otherwise noted).
CL = 30 pF for B Port and CL = 50 pF for A Port
Symbol
From
To
Typ
Min
Max
Unit
(Input)
(Output)
(Note 7)
tOSLH (Note 8)
A
B
tOSHL (Note 8)
A
B
tPS (Note 9)
A
B
tPV(HL) (Note 10)(Note 11)
A
B
tOSLH (Note 8)
B
A
tOSHL (Note 8)
B
A
tOST (Note 8)
B
A
tPS (Note 9)
B
A
tPV (Note 10)
B
A
Note 7: All typical values are at VCC = 3.3 V and TA = 25°C.
0.1
0.2
ns
0.1
0.6
0.3
1.0
ns
1.3
ns
0.1
0.7
ns
0.1
0.4
0.2
1.1
ns
0.1
1.0
ns
2.4
ns
Note 8: tOSHL/tOSLH and tOST – Output-to-Output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs
within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same
direction dither HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and
statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the
device.
Note 9: tPS – Pin or Transition skew is defined as the difference between the LOW-to-HIGH transition and the HIGH-to-LOW transition on the same pin. The
parameter is measured across all the outputs of the same chip is specified for a specific worst case VCC and temperature. This parameter is guaranteed by
design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance
seen by the device.
Note 10: tPV – Part-to-Part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device-to-device.
The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual
skew values between the GTLP output could vary on the backplane due to the loading and impedance seen by the device.
Note 11: Due to the open drain structure on GTLP outputs tOST and tPV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the
VTT and RT values on the backplane.
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