FAN3850A Datasheet, PDF (5/11 Pages) Fairchild Semiconductor – Microphone Pre-Amplifier with Digital Output

Electrical Characteristics (Continued)
Unless otherwise specified, all limits are guaranteed for T_A=25°C, V_DD=1.8V, V_IN=94dB(SPL), and f_CLK=2.4MHz.
Duty Cycle=50% and C_MIC=15pF.
Symbol
Parameter
Condition
Min. Typ.
tA
Time from CLOCK Transition
to Data becoming Valid
tB
Time from CLOCK Transition
to Data becoming HIGH-Z
tA
Time from CLOCK Transition
to Data becoming Valid
tB
fCLK
CLKdc
tWAKEUP
tFALLASLEEP
Time from CLOCK Transition
to Data becoming HIGH-Z
Input CLOCK Frequency⁽⁸⁾
CLOCK Duty Cycle⁽⁴⁾
Wake-Up Time⁽⁹⁾
Fall-Asleep Time⁽¹⁰⁾
CLOAD Load Capacitance on Data
On Falling Edge of CLOCK,
SELECT=GND, C_LOAD=15pF
On Rising Edge of CLOCK,
SELECT=GND, C_LOAD=15pF
On Rising Edge of CLOCK,
SELECT=V_DD, C_LOAD=15pF
On Falling Edge of CLOCK,
SELECT=V_DD, C_LOAD=15pF
Active Mode
f_CLK=2.4MHz
f_CLK=2.4MHz
18
43
0
5
18
56
0
5
1.0
2.4
40
50
0.35
0
0.01
Notes:
3. Pseudo-random noise with triangular probability density function. Bandwidth up to 10MHz.
4. Guaranteed by characterization.
5. Assuming that 120dB(SPL) is mapped to 0dBFS.
6. Assuming an input of -45dBV
7. Guaranteed by design.
8. All parameters are tested at 2.4MHz. Frequency range guaranteed by characterization.
9. Device wakes up when f_CLK • 300kHz.
10. Device falls asleep when f_CLK ” 70kHz.
Max.
16
16
4.0
60
2.00
1.00
100
Unit
ns
ns
ns
ns
MHz
%
ms
ms
pF
© 2010 Fairchild Semiconductor Corporation
FAN3850A • Rev. 3.0.6
Figure 3. Interface Timing
5
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