FOD073L_09 Datasheet, PDF (4/12 Pages) Fairchild Semiconductor – LVTTL/LVCMOS Compatible Low Input Current High Gain Split Darlington Optocoupler

Electrical Characteristics (Continued) (T_A = 0 to 70°C unless otherwise specified)
Isolation Characteristics
Symbol
Characteristics
Test Conditions
Min. Typ.*
I_I-O
V_ISO
R_I-O
C_I-O
I_I-I
R_I-I
C_I-I
Input-Output Insulation
Leakage Current
Withstand Insulation Test
Voltage
Relative humidity = 45%, T_A = 25°C,
t = 5 s, V_I-O = 3000 VDC (Note 3)
R_H ≤ 50%, T_A = 25°C, I_I-O ≤ 2µA,
t = 1 min. (Note 3)
Resistance (Input to Output) V_I-O = 500 VDC (Note 3)
Capacitance (Input to Output) f = 1 MHz (Notes 3, 4)
Input-Input Insulation
Leakage Current
RH ≤ 45%, V_I-I = 500 VDC (Note 5)
Input-Input Resistance
Input-Input Capacitance
V_I-I = 500 VDC (Note 5)
f = 1 MHz (Note 5)
2500
0.005
10¹²
0.7
10¹¹
0.03
*All typicals at T_A = 25°C
Max.
1.0
Unit
µA
V_RMS
Ω
pF
µA
Ω
pF
Notes:
1. Current Transfer Ratio is defined as a ratio of output collector current, I_O, to the forward LED input current, I_F, times
100%.
2. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV_CM/dt on the leading
edge of the common mode pulse signal, V_CM, to assure that the output will remain in a logic high state
(i.e., V_O > 2.0V). Common mode transient immunity in logic low level is the maximum tolerable (negative) dV_CM/dt
on the trailing edge of the common mode pulse signal, V_CM, to assure that the output will remain in a logic low state
(i.e., V_O<0.8 V).
3. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are
shorted together.
4. CI-O is measured by shorting pins 1 and 2 or pins 3 and 4 together and pins 5 through 8 shorted together.
5. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
©2004 Fairchild Semiconductor Corporation
FOD073L Rev. 1.0
4
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