FMS6366 Datasheet, PDF (4/7 Pages) Fairchild Semiconductor – Selectable YPbPr HD/SD 4:2:2 Video Filter Driver with Y, C and Composite Outputs

DATA SHEET
FMS6366
Functional Description
DC Levels
At any given time, the input signal’s DC levels must be
between 0.0V and 1.3V to utilize the optimal headroom
and to avoid clipping at the outputs. The Y channels accept
1Vpp signals with the sync tip at ground. The Pb, Pr and C
channels should be centered around 0.5V. This will ensure
that the filter will utilize the optimal headroom and avoid
clipping.
DC-Coupled Output Applications
The 220uF capacitor coupled with the 150Ω termination
forms a high pass filter that blocks the DC while passing the
video frequencies and avoiding tilt. Lower values such as
10uF cause unacceptable tilt in the output signal. By AC
coupling, the average DC level is zero. Thus, the output volt-
ages of all channels will be centered around zero.
DC coupling the output of the FMS6366 is allowable, but
not recommended. There are several trade-offs: The average
DC level on the outputs will be 2V. Each output will dissi-
pate an additional 40mW nominally. The application will
need to accommodate a 1V DC offset sync tip. Also, it is
recommended to limit one 150Ω load per output.
The FMS6366 is specified to operate with output currents
typically less than 50mA, more than sufficient for a dual
(75Ω) video load. Internal amplifiers are current limited to
a maximum of 100mA and should withstand brief duration
short circuit conditions, however this capability is not guar-
anteed.
Driving Digital Pins
The FMS6366 digital inputs are compatible with most
3.3V and 5V logic. Verify that the V_ih and V_il are within the
specified limits.
Applications
A typical application for the FMS6366 is shown in Figure 1.
DAC
A_NB
HD / N_SD
16
2
PbINA
RT1 = 75Ω
RT2 = 75Ω
RSOURCE =
RT1 || RT2
23
26
VCC
20
VCC
0.1µF
+5V
1µF
3
PbINB
4
Y1INA
PrOUT
220µF
24
75Ω
75Ω Video Cable
75Ω
RT1 = 75Ω
RT2 = 75Ω
FMS6366
5
Y1INB
Y1OUT
220µF
23
75Ω
75Ω Video Cable
75Ω
6
PrINA
RT1 = 75Ω
RT2 = 75Ω
7
PrINB
8
YC / N_AUX
9, 10, 15, 17
NC
RT1 = 75Ω
RT2 = 75Ω
12
AUXIN
RT1 = 75Ω
RT2 = 75Ω
14
Y2IN
PbOUT
220µF
22
75Ω
75Ω Video Cable
75Ω
Y2OUT
220µF
21
75Ω
75Ω Video Cable
75Ω
COUT
0.1µF
19
75Ω
75Ω Video Cable
75Ω
CVOUT
220µF
18
75Ω
75Ω Video Cable
75Ω
RT1 = 75Ω
RT2 = 75Ω
13
CIN
VSS VSS VSS VSS
11 16 25 27
Digital Delay Compensation
FMS6366
Y
Luminance
Propagation
Delay
Chroma
Pr
Pb
8-10
A/D
Shift ^8-10
Register
8-10
A/D
8-10
A/D
Video
Processing
Figure 2: Digital Delay Compensation for
anti-alias 4:2:2 filters
The Chroma filters are one half the bandwidth of the
Luminance filter therefore the propagation delay time
through the Chroma filter is longer than the Luminance filter.
In the Standard Definition (SD) case, the Chroma filter
propagation delay is typically 60 nanoseconds longer than
the Luminance filter. This is three clock cycles at 54MHz so
it is easily corrected by adding digital delay as shown in
Figure 3 and illustrated as a shift register in Figure 2. In
the High Definition (HD) setting the Chroma filter propaga-
tion delay is typically 15 nanoseconds longer than the
Luminance filter. This is one clock cycle at 74.25MHz
so it is also easily corrected by adding digital delay to the
luminance path.
Figure 1: Typical Application Diagram
4
REV. 1B September 17, 2004