FIN1104 Datasheet, PDF (4/6 Pages) Fairchild Semiconductor – LVDS 4 Port High Speed Repeater

AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
Max
(Note 3)
Units
t_PLHD
Differential Output Propagation Delay
LOW-to-HIGH
0.75
1.1
1.75
ns
t_PHLD
t_TLHD
t_THLD
t_SK(P)
t_SK(LH),
t_SK(HL)
t_SK(PP)
f_MAX
t_PZHD
Differential Output Propagation Delay
HIGH-to-LOW
R_L = 100 Ω, C_L = 5 pF,
Differential Output Rise Time (20% to 80%) V_ID = 200 mV to 450 mV,
Differential Output Fall Time (80% to 20%) V_IC = |V_ID|/2 to V_CC − (|V_ID|/2),
Pulse Skew |t_PLH - t_PHL|
Duty Cycle = 50%,
Channel-to-Channel Skew
See Figure 1 and Figure 3
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Frequency (Note 6)(Note 7)
Differential Output Enable Time
from Z to HIGH
0.75
1.1
1.75
ns
0.29
0.4
0.58
ns
0.29
0.4
0.58
ns
0.02
0.2
ns
0.02
0.15
ns
0.02
0.5
ns
400
800
MHz
2.2
5
ns
t_PZLD
t_PHZD
Differential Output Enable Time
from Z to LOW
Differential Output Disable Time
from HIGH to Z
R_L = 100 Ω, C_L = 5 pF,
See Figure 2 and Figure 3
2.5
5
ns
1.8
5
ns
t_PLZD
Differential Output Disable Time
from LOW to Z
t_DJ
LVDS Data Jitter,
V_ID = 300 mV, PRBS = 2²³ - 1,
Deterministic
V_IC = 1.2V at 800 Mbps
t_RJ
LVDS Clock Jitter,
V_ID = 300 mV,
Random (RMS)
V_IC = 1.2V at 400 MHz
Note 3: All typical values are at T_A = 25°C and with V_CC = 3.3V.
2.1
5
ns
85
135
ps
2.1
3.5
ps
Note 4: t_SK(LH), t_SK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5: t_SK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either Low-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: Passing criteria for maximum frequency is the output V_OD > 200 mV and the duty cycle is 45% to 55% with all channels switching.
Note 7: Output loading is transmission line environment only; C_L is < 1 pF of stray test fixture capacitance.
FIGURE 1. Differential Receiver Voltage Definitions and
Propagation and Transition Time Test Circuit
FIGURE 2. Differential Driver DC Test Circuit
Note A: All LVDS input pulses have frequency = 10 MHz, t_R
or t_F < = 0.5 ns
Note B: C_L includes all probe and test fixture capacitances
FIGURE 3. Differential Driver Propagation Delay
and Transition Time Test Circuit
www.fairchildsemi.com
4