FDP4030L Datasheet, PDF (4/5 Pages) Fairchild Semiconductor – N-Channel Logic Level Enhancement Mode Field Effect Transistor

Typical Electrical Characteristics (continued)
15
ID = 10A
12
9
V_DS = 6V
12V
24V
6
3
0
0
4
8
12
16
20
Q _g , GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
100
50
Limit
20
R ^DS(ON)
10
5
VGS = 10V
2 ^{SINGLE PULSE}
R_θJC= 4 ^oC/W
1
TC = 25 °C
1001µ0sµs
1ms
10ms
D1C00ms
0.5
0.5
1
3
5
10
20 30 50
V _DS , DRAIN-SOURCE VOLTAGE (V))
Figure 9. Maximum Safe Operating Area.
1000
400
Ciss
Coss
200
100
f = 1 MHz
V_GS = 0V
Crss
40
0.1
0.3
1
4
10
30
V_DS , DRAIN TO SOURCE VOLTAGE (V)
Figure 8. Capacitance Characteristics.
1000
800
600
400
200
0
0.0001
SINGLE PULSE
R _θJC = 4°C/W
T_C = 25°C
0.001
0.01
0.1
1
10
SINGLE PULSE TIME (SEC)
Figure 10. Single Pulse Maximum Power
Dissipation.
1
0.5
D = 0.5
0.2
0.2
0.1
0.05
Single Pulse
0.1
0.05
0.0001
0.001
0.01
0.1
t ₁,TIME (sec)
R _θJC (t) = r(t) * R_θJC
R_θJC = 4.0 °C/W
P(pk)
t1
t₂
T_J - T_C = P * R_θJC (t)
Duty Cycle, D = t₁ /t₂
1
10
Figure 11. Transient Thermal Response Curve.
FDP4030L Rev.B1