FDP4030L Datasheet, PDF (1/5 Pages) Fairchild Semiconductor – N-Channel Logic Level Enhancement Mode Field Effect Transistor

March 1998
FDP4030L / FDB4030L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high
density process has been especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for
low voltage applications such as DC/DC converters and
other battery powered circuits where fast switching, low
in-line power loss, and resistance to transients are
needed.
20
A,
30
V.
R_DS(ON) = 0.035 Ω
R_DS(ON) = 0.055
@
Ω
V_GS=10 V
@ V_GS=4.5V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the
need for an external Zener diode transient suppressor.
High density cell design for extremely low R_DS(ON).
175°C maximum junction temperature rating.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings T_C = 25°C unless otherwise noted
Symbol Parameter
FDP4030L
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage
I_D
Drain Current - Continuous (Note 1)
- Pulsed
(Note 1)
P_D
Total Power Dissipation @ T_C = 25°C
Derate above 25°C
T_J,T_STG Operating and Storage Temperature Range
T_L
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
THERMAL CHARACTERISTICS
R_θJC
Thermal Resistance, Junction-to-Case
R_θJA
Thermal Resistance, Junction-to-Ambient
30
±20
20
60
37.5
0.25
-65 to 175
275
FDB4030L
4
62.5
Units
V
V
A
W
W/°C
°C
°C
°C/W
°C/W
© 1998 Fairchild Semiconductor Corporation
FDP4030L Rev.B1